Level Shifter Circuit With Intrinsic NMOS Leakage Suppression
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Solution Overview
Problem
Conventional level shifters in semiconductor memory devices face challenges with high-voltage driven transistors operating under low voltage, resulting in increased time for charging and discharging nodes and high power consumption due to leakage currents.
Innovation Solution
The use of intrinsic-type NMOS transistors and control signals to rapidly charge and discharge nodes, suppressing leakage currents by controlling the operation of these transistors, thereby reducing power consumption and enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-voltage driven transistors are used in a level shifter, then the transistors can operate at high voltage levels, but the transistors experience increased threshold voltage under low voltage conditions, resulting in small drain current and increased charging/discharging time
Solution Approach 1:
The patent changes the type of NMOS transistor from conventional to intrinsic-type, fundamentally altering the transistor's electrical characteristics. Intrinsic-type NMOS transistors have zero threshold voltage, allowing them to operate effectively at low voltage levels while maintaining high drive current capability, thus resolving the contradiction between reliability and speed
2Device complexity
If conventional NMOS transistors are used to charge and discharge nodes in a level shifter, then the circuit structure is simple, but the charging and discharging time is increased due to high threshold voltage
Solution Approach 1:
The patent introduces intrinsic-type NMOS transistors which have fundamentally different electrical parameters (zero threshold voltage) compared to conventional NMOS transistors. This parameter change enables rapid charging and discharging of nodes without increasing circuit complexity, as the intrinsic-type transistors can be directly substituted into the existing circuit topology
3Adaptability or versatility
If the charge pump is not working and high voltage level equals Vdd level, then the level shifter can operate with single voltage supply, but the discharging time of output node is significantly increased
Solution Approach 1:
The use of intrinsic-type NMOS transistors with zero threshold voltage allows the transistors to remain fully conductive even when the voltage difference is small. This enables rapid discharging of the output node regardless of whether the charge pump is active or inactive, resolving the contradiction between voltage supply adaptability and discharging speed
Data Source
AI summary
A level shifter includes a pair of cross-coupled PMOS transistors, intrinsic-type NMOS transistors, an input node, a control circuit and an output node. A high voltage is supplied to the PMOS transistors. The intrinsic-type NMOS transistors and the PMOS transistors are respectively coupled in serial. The input node is configured to receive input signals. The control circuit is triggered by the voltage Vdd and is configured to generate enable signals and control signals according to the input signal. The output node is configured to output the high Voltage HV or the GND voltage as the output signal. After the node aa is charged, the transistor HVNI_1 is turned off according to the control signal SW to avoid leakage current being generated. After the node MOUT is charged, the transistor HVNI_2 is turned off according to the control signal SWb to avoid leakage current being generated.