Level Shifter Circuit Topology for 1 GHz Legacy I/O
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Solution Overview
Problem
Conventional level shifter circuits in FPGA devices face limitations in generating high-frequency output signals due to sensitivity to supply voltage variations and increased capacitive coupling, which restricts their maximum frequency to below 1 GHz, especially when supporting legacy IO standards like LVTTL and PCI.
Innovation Solution
A level shifter circuit design incorporating cross-coupled PMOS transistors with reduced width-to-length channel ratios and native NMOS transistors with threshold voltages near zero volts, along with CMOS inverter circuits, to enhance the pull-up and pull-down currents and minimize capacitive coupling, allowing for higher frequency operation up to 1 GHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifter circuits use thick oxide transistors with threshold voltages of about 0.6 volts, then the circuit can support legacy IO standards, but the gate-source voltage overdrive for NMOS transistors becomes very small (0.25 volts), making the speed sensitive to variations in supply voltage and threshold voltages
Solution Approach 1:
The patent changes the threshold voltage parameter of NMOS transistors from conventional values (about 0.6V) to near-zero values. This is achieved by using native NMOS transistors or adjusting transistor dimensions (width-to-length ratios) to obtain threshold voltages close to zero, thereby increasing the gate-source overdrive voltage and improving switching speed while maintaining compatibility with legacy standards through the use of thick oxide devices where needed
2Power
If NMOS transistors are designed with much larger width-to-length channel ratios to compensate for low gate-source overdrive, then the transistors can provide sufficient current, but the capacitive coupling between input and output nodes increases, slowing down the transition of the output signal
Solution Approach 1:
The patent changes the threshold voltage parameter of NMOS transistors from conventional values to near-zero values. This allows the transistors to provide sufficient current with smaller width-to-length ratios, thereby reducing the capacitive coupling effect and improving output signal transition speed while maintaining the required current driving capability
3Power
If the gate-source voltage overdrive for PMOS transistors is much larger than for NMOS transistors, then PMOS transistors can provide strong pull-up current, but NMOS transistors require much larger width-to-length ratios, increasing device area and complexity
Solution Approach 1:
The patent changes the threshold voltage parameter of NMOS transistors to near-zero values, which increases their gate-source overdrive voltage. This balances the current capability between PMOS and NMOS transistors, allowing both to use similar width-to-length ratios and reducing the complexity and area requirements of the level shifter circuit
Data Source
AI summary
A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.