Level Shifter Control Circuit for Low-Delay, Low-Power Switching
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Solution Overview
Problem
Conventional level shifters suffer from racing phenomena leading to long propagation delays and high power consumption, and they often create electrostatic discharge paths due to direct coupling of auxiliary pull-up devices to high voltage sources.
Innovation Solution
A level shifter design that includes a Not gate, PMOS and NMOS transistors, and a control circuit with a leakage current preventing unit and a racing problem reducing unit, which prevents current leakage and eliminates the racing problem without forming an electrostatic discharge path by controlling the PMOS transistor's state based on signal levels and using a PMOS transistor with its source coupled to the high voltage source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If cross-coupled PMOS transistors are used in a conventional level shifter, then the design is simple, but racing phenomenon occurs leading to long propagation delay and high power consumption
Solution Approach 1:
The control circuit predicts the racing condition by monitoring the voltage difference between nodes A and B, and preemptively adjusts the gate voltages of PMOS transistors P6 and P7 to prevent the racing phenomenon before it occurs, thereby reducing propagation delay
Solution Approach 2:
The control circuit continuously monitors the voltage levels at nodes A and B, and dynamically adjusts the gate voltages of the PMOS transistors based on the detected voltage difference, creating a feedback mechanism that eliminates racing and reduces propagation delay
2Device complexity
If cross-coupled PMOS transistors are used in a conventional level shifter, then the design is simple, but racing phenomenon occurs leading to high power consumption
Solution Approach 1:
The control circuit detects the racing condition by monitoring voltage differences and preemptively adjusts transistor gate voltages to prevent simultaneous conduction, thereby preventing excessive power consumption before it occurs
Solution Approach 2:
The control circuit uses feedback from voltage monitoring at nodes A and B to dynamically control the gate voltages of PMOS transistors, ensuring they do not conduct simultaneously and thus preventing power consumption spikes
3Speed
If auxiliary pull-up devices are directly coupled to high voltage source, then switching speed is improved, but electrostatic discharge path is formed causing reliability issues
Solution Approach 1:
The control circuit acts as an intermediary between the high voltage source and the PMOS transistors, carefully controlling their operation to achieve fast switching while preventing direct electrostatic discharge paths through coordinated gate voltage adjustment
Data Source
AI summary
A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.