Dual-Path Level Shifter for Low-Jitter High-Speed I/O Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing level shifters for high-speed data transmission face challenges with power consumption, robustness, reliability, and integrity issues, as well as increased jitter and signal distortion, which hinder efficient data transmission in electronic devices.
Innovation Solution
A level shifter design incorporating a main and auxiliary level shifter portion with PMOS and NMOS transistors, including a current mirror structure and switch circuits to settle internal nodes and minimize power consumption, reduces Inter Symbol Interference (ISI) and Data Dependent Jitter (DDJ), supporting high-speed data transmission from 5 Gbps to 6 Gbps with reduced power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a level shifter is designed for high speed data transmission, then transmission speed is improved, but power consumption increases
Solution Approach 1:
The level shifter dynamically adjusts its operation mode based on data patterns. During high-speed transmission, the full circuit operates to maintain speed. During low-frequency or static periods, the circuit transitions to a low-power mode where certain transistors are turned off, reducing power consumption while maintaining transmission capability when needed.
Solution Approach 2:
The invention changes the operational parameters of the level shifter circuit by selectively enabling and disabling specific transistor paths based on the frequency and pattern of incoming data. This allows the circuit to adapt its power consumption and performance characteristics to match actual transmission requirements.
2Speed
If a level shifter is designed for high speed data transmission, then transmission speed is improved, but signal distortion and jitter increase
Solution Approach 1:
The level shifter incorporates preliminary action by pre-charging and pre-discharging internal nodes before actual data transmission occurs. This ensures that when high-speed data arrives, the circuit is already in an optimal state to handle the transition, reducing jitter and signal distortion. The switch circuit settles internal nodes to predetermined values in advance.
Solution Approach 2:
The invention introduces an intermediary switch circuit that mediates between the input and output of the level shifter. This switch circuit actively controls the settling of internal nodes and manages the transition between different operational states, preventing signal distortion and jitter while maintaining high-speed transmission capability.
3Use of energy by moving object
If a level shifter operates at low frequency, then power consumption is reduced, but transmission speed decreases
Solution Approach 1:
The level shifter dynamically adapts its operational characteristics based on the frequency of incoming data. At low frequencies, the circuit enters a power-saving state by disabling certain transistor paths. When high-speed transmission is detected, the circuit dynamically switches to a high-performance mode, ensuring both power efficiency and speed capability are optimized for the current operating conditions.
4Speed
If existing level shifters are used for high speed transmission, then transmission capability is achieved, but complexity and component count increase
Solution Approach 1:
The invention merges multiple functions into a unified level shifter circuit. The main level shifter portion and auxiliary level shifter portion are integrated with switch circuits that perform multiple tasks: controlling signal flow, settling internal nodes, and managing power consumption. This consolidation achieves high-speed transmission capability while reducing overall circuit complexity compared to separate dedicated circuits for each function.
Data Source
AI summary
A level shifter includes main and auxiliary level shifters, a switch circuit and a hold circuit. The main level shifter includes NMOS and PMOS transistors in a Differential to Single Ended (D2S) structure. The auxiliary level shifter is connected to an output of the main level shifter and includes NMOS and PMOS transistors. Each of the main and auxiliary level shifters includes internal nodes. The switch circuit settles first nodes of the internal nodes to values to support high speed data transmission, and the hold circuit holds second nodes of the internal nodes to a certain value during low frequency operation. The level shifter receives a serial stream of binary values of core supply voltage, converts the serial stream of binary values from the core supply voltage to an input/output (I/O) voltage, and outputs the serial stream of binary values of the input/output (I/O) voltage.