Thick-Oxide Level Shifter Layout for Low-Voltage Reliability
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Solution Overview
Problem
Existing level shifter designs for ultra-low voltage operations face challenges in reducing circuit area and achieving sufficient reliability under high standard deviation process variations, especially when native IO components are unavailable.
Innovation Solution
A level shifter architecture utilizing thick-oxide components only, comprising specific configurations of N-type and P-type transistors, and a buffer, which generates output voltage based on shifted voltages from these transistors, effectively reducing the cross-coupled voltage and minimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If thick-oxide components are adopted for ultra-low voltage operation when native IO components are unavailable, then the level shifter can operate under ultra-low voltage conditions, but the circuit area greatly increases
Solution Approach 1:
The level shifter is divided into two independent paths: a first path containing a first thick-oxide transistor for shifting high voltage to low voltage, and a second path containing a second thick-oxide transistor for shifting low voltage to high voltage. This segmentation allows each path to be optimized independently, reducing the overall circuit area compared to a single unified design.
Solution Approach 2:
The circuit employs dynamic control through a control signal that selectively activates either the first thick-oxide transistor or the second thick-oxide transistor based on the desired voltage conversion direction. This dynamic operation allows the circuit to achieve ultra-low voltage operation only when needed, reducing the effective circuit area during normal operation.
2Ease of manufacture
If conventional level shifter architectures are used, then the design can be implemented with existing components, but reliability is insufficient under high standard deviation process variation
Solution Approach 1:
The invention changes the operational parameters of the thick-oxide transistors by introducing specific gate control mechanisms and biasing schemes that optimize the transistors' performance under ultra-low voltage conditions. This parameter optimization maintains reliability despite process variations while keeping the design implementable with standard thick-oxide components.
3Area of moving object
If transistor sizes are reduced to minimize circuit area, then the overall circuit area decreases, but the upper bound of cross-coupled voltage increases
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a controlled thick-oxide transistor that acts as a voltage regulator between the cross-coupled nodes. This intermediary component actively manages the cross-coupled voltage levels, preventing excessive voltage buildup even when transistor sizes are reduced for area minimization.
Solution Approach 2:
The circuit implements feedback control through the cross-coupled configuration where the output of each path feeds back to control the other path. This feedback mechanism automatically adjusts the operating points of the transistors to maintain stable voltage levels, allowing smaller transistor sizes without compromising voltage control.
Data Source
AI summary
A level shifter which includes an inverter, first/second/third/fourth N-type transistors, first/second P-type transistors and a buffer is provided. The inverter inverts an input voltage to generate an inverted input voltage based on a first reference voltage. The first N-type transistor has a gate receiving the input voltage. The second N-type transistor has a gate receiving the inverted input voltage. The third N-type transistor has a source coupled to a drain of the first N-type transistor. The fourth N-type transistor has a source coupled to a drain of the second N-type transistor. Gates of the first/second P-type transistors are coupled to the drains of the second/first N-type transistors, respectively, and sources of the first/second P-type transistors receive a second reference voltage. The level shifter generates an output voltage according to a shifted voltage on the drain terminal of the third N-type transistor or the drain terminal of the fourth N-type transistor.