Level Shifter for Bidirectional Data Transfer Between MPU and Memory
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Solution Overview
Problem
Existing methods for data transmission and reception between micro processing units (MPUs) and memories in programmable logic controllers (PLCs) with different operating voltages result in inefficiencies and data loss due to unidirectional communication and voltage level mismatches, particularly when multiple MPUs with different voltages share a memory.
Innovation Solution
A method involving the output of chip select and address signals by the MPU, activation signals by OR gates for data buffers, and memory access signals by output buffers to enable bidirectional data transmission and reception, with level shifting to accommodate different voltage levels, allowing data to be read and written without loss across devices with varying operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unidirectional communication method is used for data transmission between devices with different operating voltages, then voltage level mismatch is handled, but data loss occurs and communication efficiency deteriorates
Solution Approach 1:
The patent introduces a level shifter as an intermediary device between the MPU and memory to convert voltage levels. The level shifter includes first and second buffers that enable bidirectional communication by translating voltage signals between 3.3V (MPU) and 5V (memory) domains, eliminating data loss while maintaining communication efficiency.
Solution Approach 2:
The level shifter is designed to handle both read and write operations bidirectionally. It can transmit data from MPU to memory and from memory to MPU, providing universal functionality that replaces multiple unidirectional communication channels and improves overall communication efficiency.
2Adaptability or versatility
If multiple MPUs with different operating voltages share a memory, then system functionality is enhanced, but data loss and communication failures occur due to voltage mismatches
Solution Approach 1:
The level shifter acts as a voltage translation intermediary that enables multiple MPUs with different operating voltages (e.g., 3.3V and 5V) to share a common memory device. By converting voltage levels at the interface, it ensures reliable data transmission from each MPU to the memory and back, eliminating communication failures.
Solution Approach 2:
The system dynamically changes voltage parameters through the level shifter, which converts between 3.3V and 5V levels based on the direction of communication and the specific MPU involved. This parameter transformation enables multi-MPU compatibility while maintaining data integrity.
3Reliability
If bidirectional communication is implemented between devices with different operating voltages, then data transmission completeness is improved, but system complexity increases
Solution Approach 1:
The level shifter consolidates bidirectional communication functionality into a single intermediary device. It manages both voltage level conversion and signal direction control internally, providing complete data transmission without requiring separate complex circuits for each communication direction, thus limiting the increase in system complexity.
4Device complexity
If conventional unidirectional communication is used, then device complexity is reduced, but data loss occurs during transmission
Solution Approach 1:
The level shifter with its buffer structure prevents data loss by ensuring proper voltage level translation and signal integrity during bidirectional communication. The first buffer handles MPU-to-memory transmission while the second buffer handles memory-to-MPU transmission, eliminating data loss without requiring overly complex error correction mechanisms.
Data Source
AI summary
A method for transmitting and receiving data between a micro processing unit (MPU) and a memory operating with different operating voltages in a programmable logic controller (PLC) is provided. In one embodiment, the method includes outputting, by the MPU, a chip select (CS) signal and an address signal to read requested data from the memory, outputting, by an OR gate, an activation signal for activating a data input buffer, the OR gate receiving the CS signal and the address signal, and outputting, by an access signal output buffer, a memory access signal for operation of the memory, the access signal output buffer receiving the CS signal and the address signal. The method further includes outputting the requested data to the data input buffer, and outputting, by the data input buffer, the requested data to the MPU when the requested data is received by the data input buffer from the memory.