Level Shifter NAND Circuit Reliability Voltage Difference
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Solution Overview
Problem
In semiconductor devices, level shifters using P-channel MOS transistors face reliability issues due to high voltage differences across the gate and source, which can deteriorate insulation resistance and affect voltage control.
Innovation Solution
The level shifter design incorporates a NAND circuit with inverters and transistors that manage voltage supply and delay signals, reducing the voltage difference across the transistor and improving reliability by maintaining the transistor in an on-state during voltage transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a P-channel MOS transistor is used for voltage transfer in a level shifter, then the voltage transfer function is achieved, but the insulation resistance deteriorates due to high voltage difference across gate and source
Solution Approach 1:
The patent introduces a NAND circuit as an intermediary between the control signal and the P-channel MOS transistor gate. This NAND circuit processes the control signal to generate an appropriate gate control voltage, thereby mediating the voltage difference between gate and source of the P-channel MOS transistor and preventing insulation deterioration.
Solution Approach 2:
The patent changes the voltage parameters by using a NAND circuit to transform the control signal voltage levels. The NAND circuit output provides a gate voltage that maintains the P-channel MOS transistor in an on-state during voltage transfer, reducing the voltage difference across gate and source from a harmful level to an acceptable level.
2Reliability
If the transistor is turned off during voltage transfer, then voltage isolation is achieved, but voltage transfer stability is compromised
Solution Approach 1:
The patent applies preliminary action by using the NAND circuit to pre-process the control signal before it reaches the P-channel MOS transistor. The NAND circuit ensures that the gate voltage is appropriately set in advance, maintaining the transistor in an on-state during voltage transfer and preventing harmful voltage differences from occurring.
3Area of stationary object
If a simple level shifter design is used, then chip area is reduced, but control precision over transistor voltage is insufficient
Solution Approach 1:
The patent applies universality by making the NAND circuit perform multiple functions: it inverts the control signal, delays the signal timing, and most importantly, transforms the voltage levels to provide appropriate gate control for the P-channel MOS transistor. This multi-functionality achieves precise control without adding significant circuit complexity or chip area.
Solution Approach 2:
The NAND circuit serves as a compact intermediary that provides precise voltage control for the P-channel MOS transistor gate. By placing this intermediary between the control signal source and the transistor, the patent achieves accurate voltage control while maintaining a compact design that does not significantly increase chip area.
Data Source
AI summary
According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal, a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal, a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor, a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to an output terminal, a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor being connected to a second terminal of the second transistor, the second signal being applied to a gate of the third transistor, and a fourth transistor, a first terminal of the fourth transistor being connected to the second terminal of the third transistor, a second terminal of the fourth transistor being connected to the output terminal, an output terminal of the NAND circuit being connected to a gate of the fourth transistor.