Level Shifter Circuit for Deep Negative Voltage Handling
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Solution Overview
Problem
Existing level shifting circuits in integrated circuits struggle to efficiently handle both high positive and deep negative voltages, leading to voltage range violations and operational limitations, particularly in non-volatile memory applications where deep negative voltages are required.
Innovation Solution
The implementation of a level shifting circuit that eliminates simultaneous conduction of PMOS and NMOS transistors in pull-up and pull-down paths through a signal control scheme, using a switch signal and reset signal to manage voltage levels and prevent voltage range violations, allowing for deeper negative voltage handling without exceeding acceptable voltage ratings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional level shifting circuits use NMOS transistors and local charge pump to raise gate voltage, then the circuit can pass high positive voltages, but the circuit cannot handle deep negative voltages and violates acceptable voltage range characteristics
Solution Approach 1:
The level shifter is divided into separate positive voltage shifting circuitry and negative voltage shifting circuitry with distinct transistor legs. The positive path uses one set of transistors while the negative path uses another set, allowing each path to be optimized for its specific voltage range without compromising the other.
Solution Approach 2:
The circuit dynamically switches between different transistor paths based on the input voltage polarity. Control signals enable or disable specific NMOS and PMOS transistor legs depending on whether positive or negative voltage shifting is required, allowing the circuit to adapt its configuration to the current operating conditions.
2Speed
If the circuit enables quick voltage transition to full value, then switching speed improves, but simultaneous conduction of PMOS and NMOS transistors causes current contention and voltage range violations
Solution Approach 1:
Before enabling voltage transition, the control circuitry pre-configures the appropriate transistor paths by asserting control signals that enable the required NMOS or PMOS legs while disabling the opposite polarity transistors. This preliminary configuration ensures that only the correct path is active during voltage transition, preventing current contention.
Solution Approach 2:
The circuit uses control signals that respond to the input voltage state to dynamically enable or disable specific transistor paths. This feedback mechanism ensures that the circuit configuration matches the current operating conditions, preventing simultaneous conduction of conflicting transistor types.
Data Source
AI summary
A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first NMOS transistor and a first PMOS transistor in series with a first input node and a negative amplified voltage, and the second leg includes a second NMOS transistor and a second PMOS transistor in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.