Wide-Range Low-Voltage Level Shifter With NMOS Pull-Up Assist
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Solution Overview
Problem
Existing level shifters face challenges in supporting a wide voltage range, particularly with low voltage operations, leading to delays and poor switching responses due to the limitations of standard and low threshold voltage transistors, which result in inadequate headroom for transistor turn-on and increased leakage issues.
Innovation Solution
Incorporating small NMOS transistors as pull-up helpers in parallel with PMOS transistors in the level shifter, where the NMOS helper transistors' gates are driven by input voltage signals, allowing their effectiveness to scale with input and output voltage levels, and using a parallel VT architecture with differential sizing of low VT and standard VT transistors to minimize leakage and optimize circuit performance across the extended voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If standard and low threshold voltage transistors are used in level shifters, then the circuit can operate at lower voltages, but switching response becomes slow and delays increase due to inadequate headroom for transistor turn-on
Solution Approach 1:
A boost circuit is introduced as an intermediary component between the input signal and the level shifter output. This boost circuit temporarily enhances the output voltage swing, providing sufficient headroom for the transistors to switch quickly even when operating at low voltages. The boost circuit acts as a mediator that resolves the conflict between low voltage operation and fast switching by adding voltage amplitude only when needed for switching transitions.
Solution Approach 2:
The level shifter employs dynamic transistor sizing where the width of transistors is adjusted based on the operating voltage range. At lower voltages, transistors are sized larger to provide adequate drive strength and switching speed, while at higher voltages, smaller transistor sizes suffice. This dynamic adaptation allows the circuit to maintain fast switching response across the entire voltage range from 0.65V to 3.6V.
2Speed
If transistor size is increased to improve switching speed, then switching response improves, but leakage current increases
Solution Approach 1:
The circuit dynamically adjusts transistor widths based on the operating voltage. At low voltages (0.65V-1.2V), larger transistor widths are used to ensure fast switching, while at high voltages (2.4V-3.6V), smaller transistor widths are used to minimize leakage current. This dynamic sizing strategy allows the circuit to optimize both switching speed and leakage performance for each operating condition.
Solution Approach 2:
The transistor width parameter is changed according to the operating voltage range. The design specifies different transistor width ratios for different voltage domains: wider transistors for low voltage operation and narrower transistors for high voltage operation. This parameter adaptation resolves the contradiction between speed and leakage by tailoring the transistor dimensions to the specific operating conditions.
3Adaptability or versatility
If the level shifter supports a wide voltage range, then application flexibility improves, but delays increase due to adjustments needed for voltage variations
Solution Approach 1:
The level shifter uses dynamic transistor sizing adapted to different voltage ranges, allowing fast switching across the entire 0.65V to 3.6V operating range. Additionally, a boost circuit is employed that dynamically activates to provide voltage enhancement only when needed for fast switching transitions, rather than continuously. This dynamic approach maintains fast switching performance while supporting wide voltage range operation.
Solution Approach 2:
The boost circuit performs preliminary voltage enhancement before the main switching action occurs. By pre-charging or pre-enhancing the voltage levels, the circuit reduces the time required for the actual switching transition. This preliminary action allows the level shifter to maintain fast switching response even when adapting to different voltage ranges, reducing the overall switching delay.
Data Source
AI summary
A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.