Level Shifter Circuit for Reducing Drive Fights and Noise
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Solution Overview
Problem
Existing voltage level shifters face challenges in efficiently translating signals between different voltage domains due to differences in NMOS and PMOS transistor operation, leading to reliability issues and high leakage and switching currents.
Innovation Solution
The design incorporates specific configurations of NMOS and PMOS transistors, including the use of larger transistors to ensure reliable signal translation and the introduction of additional transistors to isolate and improve the performance of the level shifter, reducing drive fights and common mode noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifter designs are used, then voltage level translation is achieved, but reliability deteriorates due to drive fights and common mode noise
Solution Approach 1:
The patent introduces a dummy transistor connected between the gate and source of the output transistor as an intermediary element. This dummy transistor acts as a mediator that equalizes the voltage distribution and reduces the harmful effects of drive fights and common mode noise, thereby improving signal translation reliability without requiring additional complex circuitry.
Solution Approach 2:
The patent modifies the electrical parameters of the level shifter circuit by adjusting the size ratio between the dummy transistor and the output transistor. By changing these parameters optimally, the circuit achieves better noise immunity and reliability while maintaining the voltage level translation function, resolving the contradiction between reliability and harmful factors.
2Reliability
If additional transistors are added to improve performance, then reliability improves, but device complexity increases
Solution Approach 1:
Instead of adding multiple transistors throughout the circuit, the patent applies a localized solution by inserting a single dummy transistor at a specific critical location (between gate and source of the output transistor). This local modification targets the specific problem area of drive fights and common mode noise without increasing overall device complexity significantly.
Solution Approach 2:
The dummy transistor is merged with the existing output transistor structure by connecting it between the gate and source terminals. This merging approach allows the dummy transistor to work in conjunction with the output transistor rather than as a separate component, thereby improving reliability while minimizing the increase in device complexity.
3Reliability
If larger transistors are used to ensure reliable signal translation, then reliability improves, but area increases
Solution Approach 1:
The patent introduces a dynamic element (the dummy transistor) that actively compensates for signal degradation without requiring static enlargement of all transistors. The dummy transistor dynamically adjusts the voltage distribution during switching operations, achieving reliable signal translation with smaller overall transistor sizes and reduced circuit area.
Solution Approach 2:
By changing the parameter of the dummy transistor size relative to the output transistor, the patent achieves optimal performance with minimal area overhead. The parameter optimization allows the circuit to attain high reliability without proportionally increasing the transistor dimensions, thus resolving the contradiction between reliability and area.
Data Source
AI summary
A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.