Level Shifter Circuit With Non-Overlap Timing for Shoot-Through Reduction
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Solution Overview
Problem
Conventional level shifters experience high shoot-through current and increased power dissipation when operating at high voltages, which can lead to inefficient energy use and signal degradation due to asymmetrical rise and fall times of transistors, especially when the supply voltage exceeds the maximum transistor gate-to-source voltage.
Innovation Solution
The proposed level-shifting circuit employs a high-voltage output circuit with a pull-up and pull-down configuration, utilizing a high-side inverting buffer and low-side buffer with low-voltage devices to manage control signals and currents, along with an edge-control buffer to generate signals with controlled rise and fall times, ensuring non-overlap timing to prevent shoot-through current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional level shifter circuits are used to shift voltage levels in high-voltage systems, then voltage level shifting is achieved, but shoot-through current increases and power dissipation becomes excessive
Solution Approach 1:
The patent applies preliminary action by generating control signals with non-overlapping timing before the actual switching occurs. The first control signal is generated to have a delayed rising edge relative to the second control signal, ensuring that both high-side and low-side transistors are never simultaneously conductive. This preliminary timing arrangement prevents shoot-through current paths from forming in the first place.
Solution Approach 2:
The patent changes the timing parameter of the control signals by introducing asymmetric rise and fall times. The first control signal is configured with a delayed rising edge compared to the second control signal, creating a time offset that eliminates the overlap period where both transistors would be on. This parameter modification directly addresses the shoot-through current issue while maintaining proper voltage level shifting functionality.
2Device complexity
If conventional level shifters are used with symmetrical control signals, then simple control logic is maintained, but asymmetrical rise and fall times cause shoot-through current during transitions
Solution Approach 1:
The patent deliberately introduces asymmetry into the control signal timing by configuring the first control signal to have a delayed rising edge relative to the second control signal. This asymmetric timing arrangement creates a non-overlapping window that prevents both transistors from being simultaneously on, thereby eliminating shoot-through current. The asymmetric design is implemented through controlled signal generation rather than complex control logic.
3Power
If high-voltage transistors are used to handle high supply voltages, then voltage level shifting capability is achieved, but transistor gate oxide cannot withstand the high voltage stress
Solution Approach 1:
The patent introduces an intermediary approach by using a first control signal with delayed rising edge as a mediator between the high-side and low-side transistor control. This intermediary timing signal ensures that the high-side transistor is fully turned on before the low-side transistor begins to conduct, preventing direct high-voltage stress on the gate oxide during switching transitions and enabling reliable high-voltage operation.
Data Source
AI summary
A level-shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull-up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull-down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level-shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level-shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time.