Level Shifter Circuit With Parallel Buffers for Duty Cycle Accuracy
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Solution Overview
Problem
Integrated circuit designs face challenges in interfacing circuit blocks with different voltage requirements, leading to duty cycle distortion and increased power consumption when using level shifting circuits with reduced supply voltages.
Innovation Solution
A level shifter circuit employing first and second transistors with inverse input signals, multiplexer circuits, and parallel buffer circuits with different trip points to adjust the duty cycle and reduce power consumption by enabling specific buffer circuits based on enable signals, allowing for efficient level shifting between varying supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifting circuits are used to interface circuit blocks with different voltage requirements, then voltage level compatibility is achieved, but duty cycle distortion occurs
Solution Approach 1:
The level shifter circuit is divided into multiple parallel buffer circuits (first buffer circuit, second buffer circuit, third buffer circuit) with different trip point voltages. Each buffer circuit processes the signal independently at its optimal voltage threshold, and their outputs are combined to produce the final level-shifted signal. This segmentation allows the circuit to maintain duty cycle accuracy while adapting to different voltage domains.
2Use of energy by stationary object
If level shifting circuits operate with reduced supply voltages, then power consumption is reduced, but duty cycle distortion increases
Solution Approach 1:
The circuit dynamically selects and enables specific buffer circuits based on the operating conditions and enable signals. The down converter circuit enables specific buffer circuits to adjust the duty cycle of the output signal, allowing the system to adapt its internal configuration to maintain signal integrity while operating at reduced supply voltages.
3Manufacturing precision
If multiple buffer circuits are used to adjust duty cycle, then duty cycle accuracy is improved, but device complexity increases
Solution Approach 1:
Multiple buffer circuits with different trip points are combined in parallel configuration, sharing common input and output nodes. The buffer circuits are integrated into a unified level shifter structure with shared control logic and enable signals, reducing the overall complexity compared to separate duty cycle adjustment stages.
Data Source
AI summary
A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.