Level Shifter Signal Timing for Extended Pixel Sensing
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Solution Overview
Problem
The increasing resolution of display devices leads to longer compensation times for pixel characteristics, necessitating improved methods to compensate for changes in threshold voltage and mobility of driving transistors as they degrade over time.
Innovation Solution
A level shifter that simultaneously performs the reset of a gate driver and selection of a sensing pixel line, outputting signals in synchronization with specific edges of control signals to enhance pixel sensing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display device is increased, then the display quality is improved, but the time required for pixel compensation increases
Solution Approach 1:
The patent applies preliminary action by performing the gate driver reset and sensing pixel line selection simultaneously during the blanking period, before the actual pixel sensing operation. This overlapping of operations reduces the total compensation time while maintaining high display quality through proper signal synchronization.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining the gate driver in a ready state through simultaneous reset and line selection operations, eliminating idle time between operations. The clock signal generation is continuously controlled to match the sensing operation timing, maximizing the utilization of the blanking period for compensation tasks.
2Measurement precision
If the pixel sensing period is extended to accommodate higher resolution compensation, then the compensation accuracy is improved, but the overall frame rate decreases
Solution Approach 1:
The patent performs preliminary preparation of the gate driver and sensing line selection during the blanking period before the active display period. This allows the pixel sensing operation to start immediately when needed, extending the effective sensing period without reducing the overall frame rate by utilizing otherwise idle time.
Solution Approach 2:
The patent uses periodic clock signals generated by the level shifter to control the timing of pixel sensing operations. By synchronizing the clock signal with the blanking period and active period, the system can perform extended sensing operations during blanking intervals while maintaining the required frame rate during active display periods.
3Stability of the object's composition
If the gate driver is reset separately from sensing line selection, then the signal stability is improved, but the compensation time increases
Solution Approach 1:
The patent merges the gate driver reset operation with the sensing pixel line selection operation into a single simultaneous process. The level shifter generates control signals that perform both functions at the same time, reducing compensation time while maintaining signal stability through proper timing synchronization of the combined operations.
Solution Approach 2:
The level shifter acts as an intermediary device that coordinates and synchronizes the reset signal and sensing line selection signal. It uses clock control signals from the timing controller to generate properly timed reset and selection signals, ensuring both operations are stable and synchronized without requiring separate timing sequences.
Data Source
AI summary
Embodiments relate to a level shifter including a first circuit unit configured to output a start signal, a reset signal, and a node charge signal to a gate driver in response to a start control signal and a node charge control signal that are input from a timing controller, a second circuit unit configured to output an output erase signal and a clock shift stop signal in response to the start signal and the reset signal, and a third circuit unit configured to generate a clock signal based on a clock control signal input from the timing controller and output the generated clock signal to the gate driver in response to the output erase signal and the clock shift stop signal that are output from the second circuit unit, a display device including the same, and a method of driving the display device.


