Level Shifter Circuit With Positive Feedback for Fast Voltage Translation
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Solution Overview
Problem
Existing level shifter circuits face challenges in efficiently converting signals between different voltage domains, particularly in high-speed systems where quick signal communication across voltage domains is crucial, and they often require complex cascode circuits to handle high voltage drops, which can be stressful for transistors.
Innovation Solution
The proposed level shifter circuit employs source-follower transistors and positive feedback loops to quickly respond to voltage changes at the input node, allowing for fast switching and maintaining the switched state, and uses DEMOS transistors or cascoded transistors to handle high voltage drops, reducing stress on the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional level shifter circuits are used to convert signals between voltage domains, then signal conversion is achieved, but the switching speed is slow and transistor stress is high
Solution Approach 1:
The level shifter circuit is divided into multiple independent transistor stages (first set, second set, third set, and fourth set of transistors), each handling a portion of the voltage conversion task. This segmentation distributes the voltage stress across multiple devices and enables faster switching by reducing the burden on individual transistors.
Solution Approach 2:
Intermediate nodes are introduced between transistor stages to buffer and transfer voltage levels. These intermediate nodes act as mediators that isolate transistors from full voltage stress while maintaining signal integrity, enabling faster switching without compromising transistor reliability.
2Adaptability or versatility
If complex cascode circuits are used to handle high voltage drops, then voltage conversion capability is improved, but device complexity increases
Solution Approach 1:
The voltage conversion function is segmented across multiple transistor sets operating in series, with each set handling a portion of the total voltage drop. This approach achieves high voltage domain adaptability while keeping individual transistor stress manageable, avoiding the need for overly complex cascode structures.
Solution Approach 2:
The transistor sets are configured to perform multiple functions: voltage level conversion, signal buffering, and stress distribution. This multi-functionality reduces the need for additional specialized components, thereby managing circuit complexity while maintaining versatile voltage domain conversion capability.
3Strength
If more transistors are added to handle high voltage drops, then voltage handling capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The voltage handling capacity is distributed across four sets of transistors, each managing a portion of the total voltage. This segmentation enables the circuit to handle high voltage drops without requiring any single transistor to be oversized or specially engineered, simplifying manufacturing while maintaining strength.
Solution Approach 2:
The transistor sets are designed with similar structural characteristics and are configured in comparable arrangements. This homogeneity allows for standardized manufacturing processes and simplifies fabrication, as the same design patterns can be replicated across multiple transistor sets rather than requiring unique custom designs for each component.
Data Source
AI summary
A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.