Level Shifter Logic Isolation During Power-Up Reset

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Solution Overview

Problem

Conventional memory devices experience undesired crossing current during the power up sequence due to the behavior of the power up reset signal and the output of the level shifter, causing reliability issues as both PMOS and NMOS transistors turn on simultaneously.

Innovation Solution

Incorporating a level shifter coupled with logic, specifically a NOR gate, that isolates the output from the supply voltage during the power up sequence by using a PMOS transistor to turn OFF when the power up reset signal reaches a specific voltage level, thereby preventing both transistors from turning on simultaneously.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional level shifter is used during power up sequence, then the circuit operates normally, but crossing current occurs causing reliability issues

Engineering Contradiction:

Improvepower up sequence reliabilityVSAvoidcrossing current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The PMOS transistor is configured to turn off before the NMOS transistor turns on during the power up sequence, by monitoring the power up reset signal voltage level. This preliminary action prevents both transistors from being simultaneously on, thereby eliminating crossing current and improving power up reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The PMOS transistor acts as an intermediary element between the power up reset signal and the NMOS transistor. It monitors the voltage level and isolates the NMOS transistor from the supply voltage until the power up reset signal reaches a safe voltage level, preventing harmful crossing current

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12165693B2Circuitry including a level shifter and logic, configured to receive a power up reset signal, and associated methods, devices, and systems

Publication Date: 2024.12.10 MICRON TECHNOLOGY INC

AI summary

A device may include a level shifter including an at least one input and at least one output. The device may also include a logic circuit coupled to an output of the at least one output of the level shifter and configured to receive a power up reset signal. The logic circuit may be configured to isolate an output of the logic circuit from a supply voltage responsive to the power up reset signal and during at least a portion of a power up sequence. Associated circuits, systems, and methods are also disclosed.