Level Shifter Tie Circuit for Deterministic Power-Up Output

The patent applies preliminary action by establishing the output node in a pre-defined logic state (logic high or logic low) before the voltage domains become stable during power-up. The current-controlled tie circuit proactively drives the output to a known state using controlled current sources/sinks, preventing non-deterministic behavior before it occurs. This ensures connected circuits receive valid logic levels during the transient power-up period.

The patent introduces a current-controlled tie circuit as an intermediary element between the voltage domains and the output. This intermediary circuit, comprising PMOS and NMOS devices with controlled current sources, mediates the transition during power-up by actively managing the output node state. The intermediary controls the output behavior without requiring changes to the core level-shifting functionality.

The current-controlled tie circuit operates periodically rather than continuously - it is activated only during the power-up sequence when voltage domains are transitioning. Once the voltage domains stabilize and normal operation begins, the tie circuit is deactivated. This periodic operation ensures deterministic output during the critical power-up period while minimizing power consumption during steady-state operation.

The patent changes the operational parameters of the tie circuit dynamically. During power-up, the circuit uses controlled current sources with specific current levels to establish deterministic output states. During normal operation, the circuit parameters are adjusted or deactivated to reduce power consumption. The PMOS and NMOS devices switch between different operating states based on the power-up condition.

The patent segments the level-shifting circuit into functional modules: the core level-shifting circuit and the current-controlled tie circuit. The tie circuit is further segmented into PMOS-based current sources and NMOS-based current sinks. This segmentation allows the stability function to be isolated in a dedicated module that can be independently controlled and deactivated during normal operation, limiting the complexity impact to a specific functional block.

The current-controlled tie circuit is designed with multi-functionality to reduce overall complexity. The same PMOS and NMOS devices serve dual purposes: they provide deterministic output during power-up and can function as part of the normal level-shifting operation after power-up completes. The gate-bias control circuit provides universal control for both power-up and steady-state conditions, managing multiple functions through a single control mechanism.