Level Shifter Ramp Selection for Balanced Transition Times
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Solution Overview
Problem
Conventional level shifters exhibit asymmetrical transition times between output voltage levels, leading to inefficiencies and predictability issues in systems relying on binary inputs, as one transition time is consistently longer than the other.
Innovation Solution
A ramp selection circuit is employed to choose between the primary and inverted outputs of a level shifter, utilizing a delay circuit to select the output with the shorter transition time, thereby reducing the maximum transition time and improving efficiency and predictability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifter circuits are used, then voltage level conversion is achieved, but the transition time between voltage levels becomes asymmetrical
Solution Approach 1:
The patent applies asymmetry by introducing a delay circuit that selectively delays one of the complementary outputs based on detected transition direction. This creates an asymmetrical delay compensation mechanism that balances the overall transition times, resolving the asymmetry problem through controlled asymmetrical intervention
Solution Approach 2:
The patent employs feedback by detecting the transition direction of the input signal and using this information to control the delay circuit. The delay amount is adjusted based on the detected transition state, creating a closed-loop system that compensates for asymmetrical transition times
2Loss of energy
If conventional level shifters are used, then power domain conversion is achieved, but power losses occur during transitions
Solution Approach 1:
The level shifter circuit uses its own output signals to control the delay circuit through feedback detection. The circuit self-regulates the delay amount based on its own transition characteristics, eliminating the need for external control and enabling automatic optimization of transition timing to reduce power losses
3Productivity
If asymmetrical transition times are accepted, then circuit simplicity is maintained, but system efficiency decreases
Solution Approach 1:
The patent segments the level shifter into distinct functional blocks: the core level shifting stage, the transition detection circuit, and the delay compensation circuit. This segmentation allows each component to perform its specific function efficiently while maintaining overall system manageability and reducing the negative impact of added complexity
Data Source
AI summary
A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.