Level Shifter Circuit Using Reference Voltage for Safe I/O Scaling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional level shifter circuits face difficulties in shifting voltage levels from logic circuitry to I/O circuitry as the voltage difference increases, leading to operational issues when logic circuitry scales down, particularly due to gate oxide reliability problems and failure of transistors to activate properly.

Innovation Solution

A voltage level shifter circuit that uses a reference voltage independent of the high voltage supply, combined with I/O and logic transistors, to ensure the maximum tolerable voltage across transistors is not exceeded, allowing operation across various silicon process technologies and voltage supply values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If logic circuitry voltage is reduced to enable scaling down, then productivity and integration density are improved, but the ability to properly shift voltage levels to I/O circuitry deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidvoltage level shifting capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a reference voltage circuit as an intermediary element that mediates between the low voltage logic domain and high voltage I/O domain. This reference voltage serves as a stable intermediate reference that enables proper transistor activation and voltage level shifting without requiring the logic transistors to directly handle the full voltage difference, thus resolving the contradiction between scaled-down logic voltage and reliable voltage shifting.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If logic transistor maximum tolerable voltage is exceeded, then device complexity is reduced, but gate oxide reliability deteriorates

Engineering Contradiction:
Improvetransistor voltage toleranceVSAvoidgate oxide reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the voltage shifting function into multiple stages using a reference voltage circuit and multiple transistor levels. Instead of using a single transistor to handle the entire voltage difference (which would exceed maximum tolerable voltage), the function is divided into: (1) reference voltage generation, (2) intermediate voltage level creation, and (3) final I/O voltage output. This segmentation allows each transistor to operate within its safe voltage limits while maintaining overall system functionality.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If transistors are configured to operate at logic levels, then adaptability to voltage scaling is improved, but gate oxide reliability deteriorates

Engineering Contradiction:
Improvevoltage scaling adaptabilityVSAvoidgate oxide reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The reference voltage circuit acts as a mediator that allows logic transistors to operate at their safe voltage levels while still achieving the required high voltage output. The reference voltage provides a stable intermediate reference that enables the logic transistors to function adaptively with scaled voltages without being exposed to excessive voltage that would damage their gate oxide.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7772885B1Level shifter circuit to shift signals from a logic voltage to an input/output voltage
Publication Date: 2010.08.10 NVIDIA CORP
  • US7772885B1 patent drawing
  • US7772885B1 patent drawing
  • US7772885B1 patent drawing

AI summary

One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from the high voltage domain to a low voltage domain, where VDD_IO is the supply voltage of the high voltage domain and VDD_Logic is the supply voltage of the low voltage domain. A level shifting circuit using a combination of I/O and logic transistors avoids exceeding a maximum tolerable voltage across the gate and source of any of the transistors. The level shifting circuit operates includes a reference voltage circuit that is independent of VDD_IO, so the same level shifting circuit may be used for various VDD_IO voltages. Additionally, the voltage level shifting circuit is not sensitive to scaling of VDD_Logic and operates properly when VDD_Logic is reduced due to shrinking silicon process technology and/or is reduced for a low power application.