Flat Panel Level Shifter Circuit for Low-Leakage Signal Timing
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Solution Overview
Problem
Conventional level shifters in flat panel displays experience high power consumption and signal delay due to concurrent transistor operation during transition periods, leading to increased leakage current and uneven delay times for rising and falling signal voltages.
Innovation Solution
A level shifter design that prevents concurrent turn-on of transistors by utilizing different types of transistors and a diode-connected configuration, ensuring only one transistor is active at a time, and incorporating a capacitor to manage voltage levels, thereby reducing power consumption and equalizing delay times for signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional level shifters use multiple transistors operating concurrently during transition periods, then the signal level shifting function is achieved, but power consumption increases and signal delay occurs
Solution Approach 1:
The patent implements dynamic switching between different transistor configurations based on signal transition states. During stable periods, transistors operate in standard mode; during transition periods, the circuit dynamically reconfigures to prevent concurrent transistor operation, thereby reducing power consumption while maintaining signal integrity and consistent delay times.
Solution Approach 2:
The patent changes the operational parameters of transistors during transition periods by adjusting gate voltages and switching timing. This parameter modification ensures that transistors do not operate concurrently during critical transitions, reducing leakage current and power consumption while equalizing rise and fall delay times through controlled voltage level adjustments.
2Power
If transistors operate concurrently during transition periods, then signal level shifting is achieved, but leakage current increases
Solution Approach 1:
The circuit dynamically adjusts transistor operating states based on signal transition detection. During transition periods, the patent implements non-concurrent operation modes that minimize the overlap of active transistor states, thereby reducing leakage current paths while maintaining the necessary signal level shifting function.
Solution Approach 2:
The patent modifies transistor operating parameters during transition periods by controlling gate voltages and switching timing sequences. This parameter control prevents simultaneous conduction of multiple transistors, effectively reducing leakage current without compromising the level shifting functionality.
3Reliability
If conventional level shifters are used, then signal level shifting function is provided, but delay times for rising and falling voltages are uneven
Solution Approach 1:
The patent employs asymmetric transistor configurations where different transistor types (N-type and P-type) are strategically positioned and controlled to compensate for inherent asymmetries in rise and fall times. During transition periods, the circuit applies asymmetric control voltages and timing sequences to equalize the overall delay characteristics despite the asymmetric nature of individual transistor operations.
Solution Approach 2:
The patent implements dynamic control mechanisms that adjust transistor switching timing and voltage levels based on the current signal state. This dynamic adjustment compensates for the inherent asymmetry in transistor switching characteristics, equalizing rise and fall delay times while maintaining the level shifting function through adaptive parameter modification.
Data Source
AI summary
A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected.