Level Shifter Circuit With Balanced Pull-Up and Pull-Down Skew
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Solution Overview
Problem
Level shifter circuits often experience waveform distortion and duty ratio distortion due to imbalanced pull-up and pull-down skew, especially when dealing with high-frequency input signals, leading to inefficient voltage shifting between different power supply levels.
Innovation Solution
The proposed level shifter circuit includes a first voltage-based input circuit generating inverted and non-inverted voltages, a pull-up circuit generating currents to increase the output voltage during the rise of the non-inverted voltage, and a pull-down circuit generating currents to decrease the output voltage during the rise of the inverted voltage, ensuring balanced pull-up and pull-down operations to reduce skew and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional level shifter circuits are used, then voltage level shifting between different power supply levels is achieved, but waveform distortion and duty ratio distortion occur due to imbalanced pull-up and pull-down skew
Solution Approach 1:
The patent applies asymmetry by configuring the pull-up circuit and pull-down circuit with different circuit topologies and transistor arrangements. The pull-up circuit uses a first transistor and first capacitor configured differently from the second transistor and second capacitor in the pull-down circuit, allowing each circuit to be optimized for its specific function to compensate for inherent asymmetries in voltage switching behavior.
Solution Approach 2:
The patent changes circuit parameters by adjusting the capacitance values of the first and second capacitors, the transistor sizes (width-to-length ratios), and threshold voltages to balance the pull-up and pull-down skew. By carefully selecting these parameters, the circuit achieves symmetric switching characteristics despite using asymmetric circuit topologies.
2Speed
If high-frequency input signals are processed, then faster voltage shifting is achieved, but waveform distortion and duty ratio distortion increase due to pull-up and pull-down skew
Solution Approach 1:
The patent applies preliminary action by pre-charging and pre-discharging the capacitors during the switching process. The first capacitor is pre-charged before the pull-up operation, and the second capacitor is pre-charged before the pull-down operation, ensuring that the voltage transitions occur symmetrically and reducing skew effects during high-frequency operation.
Solution Approach 2:
The patent implements feedback by using the output signal to control the switching of transistors in both the pull-up and pull-down circuits. The inverted output signal feeds back to control the pull-down circuit, while the non-inverted output signal feeds back to control the pull-up circuit, ensuring coordinated operation and reducing waveform distortion at high frequencies.
Data Source
AI summary
A level shifter circuit is provided. The level shifter circuit includes a first voltage-based input circuit configured to generate a first voltage-based inverted voltage and a first voltage-based non-inverted voltage based on an input voltage having a first voltage as a first peak voltage; a pull-up circuit configured to generate a second voltage-based first current corresponding to the first voltage-based non-inverted voltage, generate a second voltage-based pull-up current based on the second voltage-based first current, and pull up an output voltage according to the second voltage-based pull-up current when the first voltage-based non-inverted voltage increases; and a pull-down circuit configured to generate a second voltage-based second current corresponding to the first voltage-based inverted voltage, generate a second voltage-based pull-down current based on the second voltage-based second current, and pull down the output voltage according to the second voltage-based pull-down current when the first voltage-based inverted voltage increases.