Cross-Coupled Current Mirror Level Shifter for Slew Current Cancellation
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Solution Overview
Problem
Conventional level shifters struggle with fast dv/dt switching requirements in high-voltage applications due to large parasitic capacitance and channel resistance, leading to increased current consumption and noise injection errors, which are problematic for power-sensitive applications like battery applications.
Innovation Solution
A level shifter design incorporating a low voltage domain that outputs non-overlapping current pulses and a high voltage domain with a cross-coupled current mirror circuit to mirror these pulses, reducing or cancelling common mode slew current before input to the latch, thereby minimizing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large DC biasing current is applied to ensure stable signal propagation during voltage transitions, then signal stability is improved, but current consumption increases
Solution Approach 1:
The patent uses periodic current pulses instead of continuous DC biasing current. The low-voltage domain generates non-overlapping current pulses that are mirrored to the high-voltage domain only during edge transitions (rising or falling edges), eliminating the need for continuous current flow and thus reducing power consumption while maintaining signal stability during transitions.
Solution Approach 2:
The patent extracts and eliminates the common mode slew current component from the current pulses using a differential current mirror circuit. By subtracting the unwanted common mode component, the circuit achieves stable signal propagation with reduced current requirements, addressing both reliability and energy consumption concerns.
2Device complexity
If conventional level shifter design is used in high-voltage applications, then device simplicity is maintained, but switching speed is limited due to large parasitic capacitance and channel resistance
Solution Approach 1:
The patent replaces the conventional voltage-based level shifting mechanism with a current-based mechanism. By using current pulses in the low-voltage domain that are mirrored to the high-voltage domain, the circuit overcomes the limitations of parasitic capacitance and channel resistance that plague voltage-based designs, achieving fast switching speeds (>50V/ns) while maintaining reasonable circuit complexity.
Solution Approach 2:
The patent changes the fundamental operating parameter from voltage to current. The low-voltage domain generates current pulses instead of voltage transitions, and the current mirror circuit transfers these current signals to the high-voltage domain. This parameter change enables fast switching by avoiding the charging/discharging of large parasitic capacitances inherent in voltage-based high-voltage designs.
3Speed
If current signal driving is introduced to improve propagation delay time, then switching speed is improved, but noise injection errors occur
Solution Approach 1:
The patent converts the potentially harmful common mode slew current into a beneficial differential signal. The differential current mirror circuit is designed to reject common mode components (including noise and slew current) while amplifying and transferring the differential signal component. This transforms what would be noise or error into a mechanism for achieving both fast switching and high signal accuracy.
Solution Approach 2:
The differential current mirror circuit acts as an intermediary between the low-voltage current pulses and the high-voltage latch. It conditions the current signal by eliminating common mode components and providing clean differential drive to the latch, ensuring accurate signal transfer without noise injection errors while maintaining fast propagation delay.
Data Source
AI summary
A level shifter includes: a low voltage domain configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; and a high voltage domain comprising a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The current mirror circuit includes a first mirroring path for the first current pulse and a second mirroring path for the second current pulse. The level shifter has a common mode slew current that is added to the non-overlapping first and second current pulses. The first mirroring path and the second mirroring path are cross-coupled such that the common mode slew current is reduced or cancelled before the non-overlapping first and second current pulses are input to the latch.