Level Shifter Circuit Without Input Inverter for Smaller Area
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Solution Overview
Problem
Conventional level shifters require two N-type well regions with different power domains, increasing the size of the level shifter due to the need for an input inverter to invert the input signal.
Innovation Solution
The level shifter design eliminates the input inverter by using a level shifting circuit and a voltage tracking circuit to convert input signals from one power domain to another without the need for an input inverter, utilizing only one N-type well region for the P-type transistors in the VDDPST power domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an input inverter is added to invert the input signal, then the signal conversion function is achieved, but the size of the level shifter increases due to requiring two N-type well regions with different power domains
Solution Approach 1:
The patent removes the input inverter from the conventional level shifter structure. By eliminating this component, the design avoids the need for an additional N-type well region, thereby reducing the overall area while maintaining the essential signal conversion functionality through alternative circuit configuration
Solution Approach 2:
The patent combines the functions of signal inversion and level shifting into a single integrated circuit block. By merging these previously separate functions, the design eliminates the need for distinct N-type well regions for the inverter and the level shifting transistors, reducing the total area occupied by the level shifter
Data Source
AI summary
A level shifter includes a level shifting circuit and a voltage tracking circuit. The level shifting circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to first and second voltage terminals, and tracks one with a lower level among voltages of the first and second voltage terminals to generate a control voltage. The level shifting circuit includes first and second N-type transistors. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.