Level Shifter Circuit With Snap-Back Protection for High-Voltage Nodes
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Solution Overview
Problem
Level shifting circuits face reliability concerns due to snap-back issues, particularly in NMOS devices, which can lead to catastrophic failures, especially when dealing with high voltage nodes, and require complex designs to mitigate these issues.
Innovation Solution
A level shifter circuit design that includes voltage shifter circuits and bypass circuits to manage snap-back voltages, allowing for robust pull-down and pull-up paths without intentional weakening, ensuring the voltage across sensitive devices does not exceed safe snap-back levels, even with varying output loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NMOS transistors are used in discharge circuits for high voltage nodes, then the circuit can achieve faster switching speeds, but snap-back effects cause reliability failures
Solution Approach 1:
A level shift circuit is introduced as an intermediary between the high voltage output node and the NMOS discharge transistor gate. This level shift circuit translates the high voltage node state to a safe low voltage domain signal that controls the NMOS transistor, preventing direct exposure to high voltage that causes snap-back effects while maintaining fast switching response
2Loss of time
If the discharge path is strengthened to reduce propagation delay, then switching speed improves, but snap-back voltage exceeds safe levels causing device failure
Solution Approach 1:
The discharge path is segmented into two independent stages: a first discharge path using a first NMOS transistor for initial voltage reduction, and a second discharge path using a second NMOS transistor for final voltage discharge to ground. This segmentation allows each transistor to operate within safe voltage ranges while achieving complete discharge functionality, preventing snap-back effects in either individual device
3Ease of manufacture
If standard-sized transistors are used in the level shifter, then manufacturing complexity is reduced, but the transistors may still be susceptible to snap-back effects under varying load conditions
Solution Approach 1:
The level shift circuit acts as a protective intermediary that isolates standard-sized transistors from high voltage stress. By translating high voltage node states to low voltage domain control signals, the level shift circuit enables use of conventional standard-sized transistors without exposing them to snap-back conditions, even under varying capacitive loads
Data Source
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AI summary
Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.