High-Voltage Level Shifter for Sub-1 V Memory Supplies
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Solution Overview
Problem
Conventional high-voltage level shifters are unable to operate effectively at ultra-low power supply voltages below 1 V due to the high threshold voltage of high-voltage NMOS transistors, limiting their functionality in low-power semiconductor applications.
Innovation Solution
A high-voltage level shifter circuit is designed using a combination of high-voltage P-channel metal oxide semiconductor (HVPMOS) transistors, native high-voltage N-channel metal oxide semiconductor (HVNMOS) transistors, and low-voltage N-channel metal oxide semiconductor (LVNMOS) transistors, with specific connections and biasing to enable operation at voltages as low as 1 V, utilizing a common gate bias and dual power supply configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional high-voltage NMOS transistors are used in high-voltage level shifters, then the transistors can handle high voltage, but the threshold voltage is too high (about 0.8 V to 1.0 V) to operate at ultra-low power supply voltages below 1 V
Solution Approach 1:
The patent divides the NMOS transistor into two series-connected transistors: a first low-voltage NMOS transistor and a second high-voltage NMOS transistor. This segmentation allows the gate oxide to experience only low voltage (protecting it from breakdown) while the drain experiences high voltage (enabling high-voltage operation). The combined structure effectively creates a high-voltage transistor that can operate at ultra-low supply voltages by separating the voltage stress functions.
Solution Approach 2:
Different parts of the transistor structure are assigned different voltage ratings: the gate oxide region is protected with low-voltage transistors while the drain region handles high voltage. This local differentiation of voltage tolerance allows the transistor to simultaneously achieve high-voltage handling capability and ultra-low voltage operability.
2Productivity
If the threshold voltage of high-voltage NMOS transistor is increased to improve discharge rate, then discharge performance improves, but the transistor cannot operate at lower supply voltages
Solution Approach 1:
The patent segments the discharge function across two transistors in series: the first low-voltage NMOS transistor provides the necessary discharge current at ultra-low voltages, while the second high-voltage NMOS transistor handles the high-voltage discharge requirement. This segmentation resolves the contradiction by distributing the discharge function across devices with complementary voltage characteristics.
3Reliability
If conventional high-voltage level shifters are used, then high voltage level shifting is achieved, but the circuit cannot function at supply voltages below 1 V
Solution Approach 1:
The patent applies segmentation to the NMOS transistor structure, dividing it into series-connected low-voltage and high-voltage transistors. This enables the level shifter to maintain high-voltage level shifting capability while adapting to ultra-low power supply voltages below 1 V, thereby resolving the contradiction between reliability and adaptability.
Solution Approach 2:
The patent changes the voltage parameters of the transistor structure by using series connection to distribute voltage stress. This parameter transformation allows the circuit to operate reliably at both high output voltages and ultra-low supply voltages, achieving both high voltage level shifting and ultra-low voltage adaptability.
Data Source
AI summary
A high voltage level shifter includes a first high-voltage P-channel metal oxide semiconductor (HVPMOS) transistor, a second HVPMOS transistor, a discharge transistor having a first native high-voltage N-channel metal oxide semiconductor (HVNMOS) transistor and a first low-voltage N-channel metal oxide semiconductor (LVNMOS) transistor connected in series, and an avalanche transistor having a second HVNMOS transistor and a second LVNMOS transistor connected in series.