Capacitive-Coupled Level Shifter for Fast Two-Domain Switching

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing level shifter circuits for non-volatile memory devices, such as PCM memories, fail to meet requirements for fast level transitions, low power consumption, small area occupation, and parallel operation in medium-voltage and high-voltage domains, leading to inefficiencies and potential current cross-conductions.

Innovation Solution

A level shifter circuit design that includes an input stage for medium-voltage shifting, a high-level shifting stage with simultaneous output transitions, and a reset generation stage, utilizing latching units, capacitive coupling, and decoupling units to achieve fast and efficient voltage shifting with reduced energy consumption and minimal area occupation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional level shifter circuits are used to interface low-voltage and high-voltage circuit portions, then voltage level shifting is achieved, but power consumption increases and transition speed decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidtransition speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The level shifter circuit is divided into multiple independent stages: a first level shifter for medium-voltage domain shifting and a second level shifter for high-voltage domain shifting. Each stage operates independently with its own transistor pairs and control signals, allowing optimized power consumption and transition speed for each voltage domain without compromising the other.

Inventive Principle:

Principle #1Segmentation

2Area of stationary object

If conventional level shifter circuits are used, then voltage shifting is achieved, but area occupation increases

Engineering Contradiction:

Improvearea occupationVSAvoidflexibility for different voltage values

Core Design Contradiction:

Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The level shifter circuit is designed with universal control mechanisms that can adapt to different voltage values. The control signals and transistor configurations are structured to handle variable supply voltages (Vdd1 for medium-voltage domain, Vdd2 for high-voltage domain) without requiring separate circuit designs, thus reducing area occupation while maintaining flexibility for different voltage specifications.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If level shifting operations are performed sequentially in medium-voltage and high-voltage domains, then circuit complexity is reduced, but delays increase causing current cross-conductions

Engineering Contradiction:

Improvecircuit complexityVSAvoidcurrent cross-conduction prevention

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The circuit is designed to prepare and pre-charge necessary nodes before the actual level shifting operation. Control signals are generated in advance to ensure that transistors are properly biased and ready for simultaneous switching in both medium-voltage and high-voltage domains, preventing current cross-conductions while maintaining manageable circuit complexity through systematic signal sequencing.

Inventive Principle:

Principle #10Preliminary action

4Speed

If fast level transitions are implemented, then transition speed improves, but power consumption increases

Engineering Contradiction:

Improvelevel transition speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The level shifter circuit employs periodic control signals to manage the switching transitions. By using clocked control signals that periodically enable and disable transistor pairs in a coordinated manner, the circuit achieves fast transitions only when necessary, while remaining in low-power steady states during idle periods, thus balancing transition speed with power consumption.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentEP3540737B1Level shifter circuit having improved efficiency and two-domain level shifting capability, in particular for use in a memory device

Publication Date: 2020.12.30 STMICROELECTRONICS SRL

Figure 1
Figure 2~8
Figure 3

AI summary

A level shifter circuit (1), to shift an input signal (LV_IN), switching within a first voltage range, to generate at least a first output signal (HV_OUT), correspondingly switching within a second voltage range, higher than the first voltage range, having: a latching core (10) with latching input and output terminals (L_IN, L_OUT) and having a supply line (LS_TOP) designed to be supplied by a supply voltage (VPH) and a reference line (LS_BOT) designed to be coupled to a reference voltage (SHIFTED_GND); capacitive-coupling elements (13a-13b) coupled to the latching input and output terminals of the latching core (10); a driving stage (16) to bias the capacitive-coupling elements (13a-13b) with biasing signals (CP1_BOT-CP4_BOT) generated based on the input signal (LV_IN); and a decoupling stage (14, 15), driven by the driving stage (16) through the capacitive-coupling elements (13a-13b), to decouple the supply line (LS_TOP) from the supply voltage (VPH) and the reference line (LS_BOT) from the reference voltage (SHIFTED_GND) during switching of the input signal.