Multi-Stage Level Shifter for High-Voltage Down-Shifting
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Solution Overview
Problem
Existing level shifters for down-shifting voltage levels in mixed-voltage circuits require transistors with thicker gate dielectrics and higher threshold voltages, which complicates circuit design and fabrication.
Innovation Solution
A level-down shifter design that uses two parallel branches with a stack of N complementary transistor pairs (CMOS pairs) biased with an intermediate voltage, allowing the voltage level of the input signal to be stepped down without the need for transistors with thicker gate dielectrics or higher threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors with thicker gate dielectrics and higher threshold voltages are used to make the circuit tolerant to higher voltages, then the circuit can handle higher voltage domains, but circuit design and fabrication become more complex and costly
Solution Approach 1:
The voltage translation function is segmented across multiple transistor stages (first transistor stage, second transistor stage, third transistor stage) instead of requiring a single high-voltage transistor. Each stage handles a portion of the voltage translation, allowing the use of standard-voltage transistors throughout the circuit while achieving overall high-voltage tolerance.
Solution Approach 2:
An intermediate voltage node is introduced between the high-voltage input and the low-voltage output domains. This intermediate node acts as a mediator, allowing voltage translation to occur in steps through conventional transistors rather than requiring direct high-voltage transistor operation.
2Reliability
If transistors with thicker gate dielectrics and higher threshold voltages are used to make the circuit tolerant to higher voltages, then the circuit can handle higher voltage domains, but fabrication becomes more complex and costly
Solution Approach 1:
All transistors in the circuit use the same gate dielectric thickness and threshold voltage characteristics (standard-Vth transistors with typical gate dielectrics). This homogeneous approach simplifies fabrication processes and reduces manufacturing costs compared to circuits requiring mixed transistor types with different voltage ratings.
Solution Approach 2:
The voltage handling function is segmented across multiple standard-voltage transistor stages, allowing the use of uniform transistor specifications throughout the circuit. This segmentation enables standard fabrication processes to be used without requiring specialized high-voltage transistor manufacturing.
3Device complexity
If a single-stage voltage translator is used, then the circuit is simpler, but it cannot effectively down-shift voltage from high voltage domains to low voltage domains
Solution Approach 1:
The voltage down-shifting function is divided into multiple sequential stages, each performing a portion of the voltage translation. This segmentation enables effective voltage domain conversion while keeping individual transistor operations within safe voltage limits, achieving both functionality and reliability.
Solution Approach 2:
The voltage translation is achieved by adding a temporal dimension through multiple sequential stages rather than attempting single-stage conversion. This multi-stage approach transforms the voltage down-shifting problem from a single-step challenge into a series of manageable steps, each operating within conventional voltage ranges.
Data Source
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AI summary
In an aspect, there is provided a level shifter (1) for down-shifting a voltage level of a digital input signal (LDS_IN), comprising: a first branch (10) and a second branch (20), each comprising: an input (13, 21) configured to receive the digital input signal; a high-side transistor (130, 230) having a first current terminal coupled to a main supply voltage rail (2VDD), a second current terminal coupled to a first node (10a, 20a) of the respective branch, and a gate coupled to the input; a low-side transistor (110, 210) having a first current terminal coupled to a reference voltage rail (VSS), a second current terminal coupled to a second node (10b, 20b) of the respective branch, and a gate coupled to the second node (20b, 10b) of the other branch, wherein the second node of the first or second branch is an output (LDS_OUT) of the level shifter; and a stack of N transistor pairs (121, 221) coupled in series between the first and the second nodes, wherein each transistor pair comprises an nMOSFET, and a pMOSFET, the nMOSFET being subsequent to the pMOSFET as seen from the first node to the second node, wherein gates of each respective transistor pair of the stack are configured to be biased by a respective bias voltage (VDD) of a level intermediate the main supply voltage and the reference voltage.