Level Shifter Circuit for GaN Dead-Time Voltage Headroom

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Solution Overview

Problem

Power converters using GaN transistors face voltage headroom issues during dead time, preventing reliable propagation of gate drive signals due to negative voltages at the switching node, especially when using bootstrap capacitors.

Innovation Solution

A level shifter with a voltage headroom circuit that includes a current pulse generation circuit, latch, and current mirror, coupled with diodes and additional current injection paths to maintain sufficient voltage headroom independent of the electric potential difference, ensuring robust driving of high-side GaN switches even at negative voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a bootstrap capacitor is used to create a floating voltage domain to drive high-side power switches, then the high-side power switches can be properly driven, but the bootstrap node voltage follows the switching node voltage and falls to a level close to ground during dead time, causing insufficient voltage headroom for the level shifter to propagate control signals

Engineering Contradiction:
Improvereliability of high-side power switch drivingVSAvoidease of signal propagation through level shifter
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The level shifter is divided into two independent voltage domains: a first voltage domain (VDD1, GND1) for control signal input and a second voltage domain (VDD2, GND2) for high-side driver output. The GND2 is coupled to the switching node while VDD2 maintains a fixed potential through the voltage headroom circuit. This segmentation allows each domain to operate independently, solving the voltage headroom issue while maintaining reliable high-side switch driving.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The voltage headroom circuit acts as an intermediary between the floating bootstrap voltage domain and the ground-referenced control domain. It includes a first circuit portion that maintains VDD2 at a fixed potential difference above GND2, and a second circuit portion that generates a compensating voltage to offset the negative swing of GND2, thereby maintaining sufficient voltage headroom for signal propagation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If GaN transistors are used to implement the low-side power switch without a body diode, then switching speed is improved, but the switching node is forced to more negative voltages (−2V to −5V) during dead time, exacerbating the voltage headroom loss for the level shifter

Engineering Contradiction:
Improveswitching speed of power switchesVSAvoidease of signal propagation through level shifter
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The voltage headroom circuit serves as an intermediary that decouples the level shifter operation from the negative voltage swings at the switching node. By maintaining VDD2 at a fixed potential difference above GND2 and generating compensating voltage, it ensures sufficient voltage headroom even when the switching node reaches −2V to −5V, allowing fast GaN switches to operate without compromising signal propagation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The circuit dynamically adjusts voltage parameters to maintain operational integrity. The voltage headroom circuit monitors and compensates for changes in the switching node voltage, adjusting the compensating voltage to maintain adequate voltage headroom across the full range of negative voltages (0V to −8V) that occur during dead time with GaN transistors.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12597928B2Level shifter for power electronics circuits
Publication Date: 2026.04.07 INFINEON TECH AUSTRIA AG
  • US12597928B2 patent drawing
  • US12597928B2 patent drawing
  • US12597928B2 patent drawing

AI summary

A level shifter includes: a current pulse generation circuit coupled to a first supply rail and a first (ground) reference rail and configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; a latch and a current mirror circuit coupled to a second supply rail and a second reference rail and configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active, the second reference rail; and a voltage headroom circuit configured to mitigate voltage headroom loss between the second supply rail and the first reference rail, independent of an electric potential difference of the second reference rail. A power electronics circuit that includes the level shifter is also described.