Level-Shifting Buffer Circuit for Wide Input Voltage Range

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Solution Overview

Problem

Modern circuit implementations face conflicting performance requirements, such as needing a wide input voltage range and minimal quiescent current draw, which are often in opposition to each other, particularly in battery-powered devices where components may be subjected to voltages exceeding their rated specifications, risking damage and reducing battery life.

Innovation Solution

A buffer circuit is designed with a level shifter that shifts the voltage level of input signals from zero to a digital supply voltage to a reference voltage plus a threshold voltage, protecting components from excessive gate-to-source voltage and minimizing current draw by using a signal generator and comparator to generate control signals based on input voltage differences, allowing the circuit to operate across a wide voltage range while maintaining low quiescent current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the circuit operates with a wide input voltage range, then adaptability is improved, but quiescent current draw increases

Engineering Contradiction:
Improveinput voltage rangeVSAvoidquiescent current draw
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The circuit dynamically adapts its operating mode based on input voltage conditions. The output buffer switches between full-swing and reduced-swing modes, and the level shifter adjusts its voltage translation range according to the input voltage level, enabling the circuit to maintain low quiescent current while supporting a wide input voltage range from 1.8V to 5.5V

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit changes its operational parameters based on input voltage conditions. The comparator generates control signals that modify the operating point of the output buffer and level shifter, allowing the circuit to optimize its current consumption characteristics across different voltage ranges while maintaining full functionality

Inventive Principle:
Principle #35Parameter changes

2Reliability

If components are protected from excessive voltage, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvecomponent protectionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The level shifter acts as an intermediary between the input signal and the output buffer, translating voltage levels to ensure that the output buffer and other components never experience gate-to-source voltages exceeding their maximum ratings. This intermediary structure protects components without requiring complex protection circuits

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The comparator monitors the input voltage and generates feedback control signals (LMODE) that adjust the operation of the output buffer and level shifter. This feedback mechanism automatically adapts the circuit to protect components from over-voltage conditions while maintaining simplicity through automatic control

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11139807B2Buffer circuit
Publication Date: 2021.10.05 TEXAS INSTRUMENTS INC
  • US11139807B2 patent drawing
  • US11139807B2 patent drawing
  • US11139807B2 patent drawing

AI summary

A circuit that includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.