Level-Shifting Circuit Using Cascode Post-Driver for High-Voltage I/O

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Solution Overview

Problem

Integrated circuits face challenges in converting low voltage swing signals to high voltage swing signals recognizable by external circuits, as existing I/O circuits require both low-voltage and high-voltage transistors, leading to inefficiencies and increased die space usage.

Innovation Solution

The implementation of a cascode transistor post-driver stage in the I/O circuit, where P-type and N-type transistors are biased with source-gate and gate-drain voltages equal to or less than the power supply voltage, allowing the circuit to operate using low-voltage transistors without the need for high-voltage I/O transistors, and utilizing control signal generation units and parking circuits to manage voltage levels and transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If high voltage transistors are used to handle large voltage swing signals, then signal conversion capability is improved, but die space occupancy increases

Engineering Contradiction:
Improvesignal conversion capabilityVSAvoiddie space
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The I/O circuit is divided into multiple stages: a core transistor stage for low voltage swing signal processing and a cascode transistor post-driver stage for high voltage swing signal generation. This segmentation allows each stage to be optimized independently, with core transistors sized appropriately for low voltage operation and cascode transistors handling the voltage level conversion, thereby reducing the overall die space required compared to using a single large high voltage transistor

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cascode transistors serve as an intermediary between the low voltage core transistors and the high voltage external circuit. The cascode stage acts as a buffer that converts the low voltage swing output from the core transistors into a high voltage swing signal suitable for external circuits, allowing the core transistors to remain small while still achieving high voltage signal output

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If core transistors are sized to handle low voltage swing signals, then low voltage signal processing is improved, but high voltage signal handling capability deteriorates

Engineering Contradiction:
Improvelow voltage signal processing efficiencyVSAvoidhigh voltage signal handling capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The circuit functionality is segmented into two distinct stages: the core transistor stage optimized for low voltage swing signal processing with appropriately sized transistors for that function, and the cascode post-driver stage that handles the voltage level conversion to high voltage swing. This segmentation allows core transistors to be sized efficiently for low voltage operation without needing to be oversized for high voltage capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cascode transistors are dynamically controlled through biasing circuits that adjust their operating point based on the input signal conditions. This dynamic operation allows the cascode stage to effectively transfer the low voltage swing signal from the core transistors and convert it to a high voltage swing output, providing high voltage signal handling capability only when needed in the output stage

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10673437B2Level shifting circuit and method
Publication Date: 2020.06.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10673437B2 patent drawing
  • US10673437B2 patent drawing
  • US10673437B2 patent drawing

AI summary

A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.