Level Shifting Decoder Bypasses Negative Shifter for Read Speed
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Solution Overview
Problem
Existing memory systems face challenges in efficiently accessing and decoding memory addresses due to the large number of row and column lines, leading to delays in read operations, which affect overall system performance.
Innovation Solution
The implementation of a circuit and method utilizing positive and negative level shifters coupled with a buffer and decode logic, where the negative level shifter is bypassed during read operations to shorten the critical path, allowing only the positive level shifter to handle address signals, thereby speeding up read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both positive and negative level shifters are used in the decoder circuit, then the memory system can support multiple operations (read, write, erase), but the critical path delay increases during read operations
Solution Approach 1:
The circuit dynamically configures the level shifter path based on the operation type. During read operations, the negative level shifter is disabled and the signal flows only through the positive level shifter. During write and erase operations, both positive and negative level shifters are enabled. This dynamic reconfiguration reduces the critical path delay for read operations while maintaining full operational capability.
Solution Approach 2:
The negative level shifter is extracted from the critical signal path during read operations by disabling it. This removes the unnecessary delay component from the read path while preserving its functionality for write and erase operations where it is still needed.
2Speed
If the negative level shifter is bypassed during read operations, then the read speed increases, but the circuit complexity increases due to control logic
Solution Approach 1:
The control logic unit performs multiple functions: it determines the operation type (read, write, erase), selects the appropriate level shifter path, and controls the switching of the negative level shifter. This multi-functional approach consolidates control complexity into a single unit that manages all operation modes, rather than having separate control circuits for each function.
3Device complexity
If both level shifters are always enabled, then the circuit structure is simpler, but the read operation performance deteriorates due to increased delay
Solution Approach 1:
The circuit transitions from a static configuration where both level shifters are always enabled to a dynamic configuration where the negative level shifter is selectively enabled or disabled based on the operation type. This dynamic approach optimizes read operation throughput by removing unnecessary delay while maintaining the ability to handle all memory operations.
Data Source
AI summary
According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.