Resettable Level-Shifting Latch With Single-Stage Data Transfer
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Solution Overview
Problem
Existing level shifters in integrated circuits with different voltage domains suffer from multiple delay stages, which hinder efficient data transfer between circuits operating under different voltage domains.
Innovation Solution
A resettable level shifting latch is introduced, integrating level shifter and resettable latch functions to achieve a single device delay between input and output signals, reducing the number of delay stages by combining reset and output inverter functionalities within a single device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate level shifter and latch devices are used, then the circuit can perform level shifting and latching functions, but the number of delay stages increases
Solution Approach 1:
The patent combines the level shifter and resettable latch into a single integrated device. The level shifter circuitry transforms input data from a first voltage domain to a second voltage domain, while the resettable latch circuitry simultaneously performs latching and reset operations on the same transformed data, eliminating the need for separate delay stages between these functions.
Solution Approach 2:
The integrated device performs multiple functions within a single unit: level shifting (voltage domain transformation), latching (data storage), and reset (clear operation). This multi-functionality reduces the overall circuit complexity and minimizes the number of discrete components required, directly addressing the contradiction between functionality and delay stages.
2Reliability
If multiple delay stages are used in level shifters, then comprehensive voltage domain transformation and control is achieved, but the data transfer rate decreases
Solution Approach 1:
The patent merges the level shifting operation with the latching operation into a single synchronized process. The output of the level shifter is directly fed into the latch without intermediate delay stages, ensuring that voltage domain transformation and data storage occur in tight integration, thereby maintaining high data transfer rates while ensuring reliable voltage domain transformation.
Data Source
AI summary
An apparatus, including: a level shifter configured to: receive an input data signal in a first voltage domain; receive a reset signal in a second voltage domain; and generate an intermediate signal in the second voltage domain based on the input data signal and the reset signal; and a resettable latch configured to generate an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.