Level-Shifting MOS Layout With Thickened Isolation for ESD Withstand
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Solution Overview
Problem
Level-shifting MOS transistors in power electronics face issues with compromised layout integrity and reduced voltage withstand capability due to charge accumulation and strong electrostatic fields at the junctions, particularly during electrostatic discharge (ESD) testing.
Innovation Solution
The level-shifting device structure incorporates a thickened isolation structure near the doped region of the MOS transistor, with an arc-shaped junction and increased thickness to reduce charge accumulation and minimize electric field peaks, enhancing the voltage withstand capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level-shifting MOS transistor is used to connect high-voltage and low-voltage circuits, then signal level shifting is achieved, but layout integrity is compromised and voltage withstand capability is reduced due to charge accumulation and strong electrostatic fields at the junctions
Solution Approach 1:
The isolation structure is divided into multiple regions with different thicknesses: a first region with greater thickness adjacent to the drain region and a second region with lesser thickness adjacent to the source region. This segmentation allows the structure to provide enhanced voltage withstand capability where needed (near the drain) while maintaining layout integrity and reducing unnecessary complexity in other areas.
Solution Approach 2:
The isolation structure exhibits non-uniform thickness distribution, with the first region having greater thickness specifically positioned adjacent to the drain region where electrostatic stress is highest. This local quality enhancement addresses the voltage withstand capability issue at the critical location without compromising overall layout integrity or adding unnecessary complexity throughout the entire structure.
2Reliability
If the isolation structure thickness is increased to reduce charge accumulation, then voltage withstand capability improves, but device area and manufacturing complexity increase
Solution Approach 1:
The isolation structure is designed with varying thickness where the first region has greater thickness adjacent to the drain region to reduce charge accumulation and enhance voltage withstand capability. The second region has lesser thickness adjacent to the source region, minimizing the overall device area while maintaining reliability where it is most needed.
Solution Approach 2:
The isolation structure is segmented into regions of different thicknesses, allowing the greater thickness (and associated area) to be concentrated only where voltage withstand capability is critical (near the drain), rather than uniformly increasing the area across the entire device.
3Reliability
If the isolation structure is thickened near the doped region, then charge accumulation is reduced and electric field peaks are minimized, but manufacturing precision requirements increase
Solution Approach 1:
The isolation structure is segmented into a first region with greater thickness adjacent to the drain region and a second region with lesser thickness adjacent to the source region. This segmentation concentrates the manufacturing precision requirements to specific critical areas rather than requiring uniform high precision across the entire structure, making the manufacturing process more feasible.
Solution Approach 2:
The non-uniform thickness distribution localizes the enhanced isolation (and associated precision requirements) to the first region adjacent to the drain region where electrostatic stress is highest. The second region has reduced thickness with correspondingly reduced precision requirements, overall making manufacturing more achievable while maintaining electrostatic discharge resistance where it matters most.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced isolation structure improves the MOS transistor's voltage withstand capability and integrity, addressing the issues of layout compromise and electrostatic damage, thereby improving reliability and performance.
Implementation Method 1
strong electrostatic fields at the junctions
Implementation Method 2
charge accumulation and strong electrostatic fields
Data Source
AI summary
A level-shifting device structure can include: a level-shifting MOS transistor located in a semiconductor region, where the level-shifting MOS transistor comprises a source region, a drain region, and a doped region; an isolation structure extending from both sides of the doped region to form a closed ring shape, in order to divide the semiconductor region into a high-voltage side region enclosed by the isolation structure and a low-voltage side region located outside the isolation structure; and where the drain region is disposed in the high-voltage side region, and the source region is disposed in the low-voltage side region.