Integrated Level-Shifting Multiplexer for High-Speed Power Domain Crossing
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Solution Overview
Problem
Existing level-shifting multiplexers face challenges in operating at high data rates due to power domain boundary crossings, which reduce data reading speed, and require significant area when multiple storage devices are involved, leading to timing issues and increased complexity.
Innovation Solution
A level-shifting multiplexer that integrates both level-shifting and multiplexing functions, using pull-up and pull-down circuits with select signals to manage node states across power domains, reducing area and mitigating timing problems by eliminating the need for separate level shifters for each storage device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate level shifters are used for each storage device, then power domain boundary crossings are facilitated, but circuit area increases and timing issues worsen
Solution Approach 1:
The patent combines the level-shifting function and multiplexing function into a single integrated circuit. The level-shifting multiplexer includes input stages for multiple storage devices, where each input stage performs both signal selection and level-shifting operations simultaneously, eliminating the need for separate level shifters for each storage device and reducing overall circuit area.
Solution Approach 2:
The level-shifting multiplexer is designed as a universal circuit that can handle signals from multiple storage devices through a single unit. The circuit uses common pull-up and pull-down circuits shared among all input stages, allowing one circuit to serve multiple functions: multiplexing signals from different storage devices and level-shifting them to different power domains simultaneously.
2Reliability
If separate level shifters are used for each storage device, then power domain communication is enabled, but data reading speed decreases
Solution Approach 1:
By merging level-shifting and multiplexing functions into a single circuit, the patent reduces the number of signal transmission stages and intermediate nodes. This integration shortens the signal path and reduces the number of timing-critical crossings, thereby improving data reading speed while maintaining power domain communication capability.
3Reliability
If multiple separate level shifters are used, then power domain boundary crossings are supported, but circuit complexity increases
Solution Approach 1:
The patent reduces circuit complexity by combining multiple level-shifting circuits into a single level-shifting multiplexer. The integrated design uses shared pull-up and pull-down circuits that are controlled by select signals, eliminating redundant components and simplifying the overall circuit architecture while maintaining the ability to handle multiple power domains.
4Area of stationary object
If integrated level-shifting multiplexer is used, then area is reduced and timing issues are mitigated, but power domain boundary crossing capability must be maintained
Solution Approach 1:
The level-shifting multiplexer is designed as a universal circuit that maintains power domain boundary crossing capability through its integrated architecture. Each input stage includes transistors configured to perform level-shifting operations, and the common pull-up/pull-down circuits are designed to handle voltage transitions across power domain boundaries, ensuring reliability is maintained despite area reduction.
Data Source
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Figure 3
Figure 4A
AI summary
Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.