Level Shifting Output Circuit With Overvoltage Protection
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Solution Overview
Problem
In advanced technology nodes like 5 nm, the voltage difference between core and I/O domains increases, making it challenging to design multi-voltage I/O circuits that can safely operate without causing overvoltage stress to transistors, as thick oxide devices can no longer tolerate voltages greater than 1.5V across their terminals while I/O supply voltages remain at 1.8V.
Innovation Solution
A level shifting output circuit is designed with a driver circuit that uses a second supply voltage higher than the core voltage, along with protection transistors and intermediate reference voltages (VREFH and VREFL) to avoid overvoltage conditions by controlling the turn-on voltages of output driver transistors and biasing gate voltages, ensuring safe operating conditions for transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick oxide devices are used to tolerate high I/O supply voltages (1.8V), then the devices can operate at I/O domain supply voltages, but the devices cannot tolerate voltages greater than 1.5V across their terminals in technology nodes like 5nm and below
Solution Approach 1:
The output circuit is divided into multiple transistor stacks (first output driver transistor stack, second output driver transistor stack) with intermediate nodes. Each stack handles a portion of the voltage difference between core voltage (0.75V) and I/O voltage (1.8V), ensuring that no single transistor experiences voltage overstress exceeding 1.5V.
Solution Approach 2:
Intermediate reference voltages (VREFH and VREFL) are introduced as mediator voltage levels between the core voltage domain and I/O voltage domain. These intermediate voltages serve as biasing points for the transistor gates, enabling controlled voltage transitions without direct exposure to full voltage differences.
2Ease of operation
If the voltage difference between core voltage domain and I/O supply domains is reduced, then multi-voltage I/O design becomes easier, but the core voltage cannot scale down to maintain performance in advanced technology nodes
Solution Approach 1:
The circuit uses variable reference voltages (VREFH and VREFL) that can be adjusted based on the operating conditions. By dynamically changing the biasing voltages applied to transistor gates, the circuit adapts to different voltage differences between core and I/O domains, maintaining safe operation across varying conditions.
Solution Approach 2:
The output circuit employs dynamic control of transistor switching states based on input signals and reference voltage comparisons. The circuit transitions between different operational states (high output, low output, high-impedance) by dynamically adjusting which transistors are conductive, allowing flexible adaptation to different voltage conditions.
3Adaptability or versatility
If standard devices are used that can only handle up to 1.65V across their terminals, then device compatibility is maintained, but the devices cannot safely operate with I/O supply voltages of 1.8V
Solution Approach 1:
The circuit design incorporates protective transistor stacks and intermediate voltage nodes that preemptively prevent voltage overstress before it can damage the devices. By structuring the circuit to distribute voltage differences across multiple components, the design cushions standard devices from experiencing dangerous voltage levels.
Solution Approach 2:
Intermediate reference voltages and protective transistor stacks act as mediators between the 1.8V I/O supply and the standard devices that can only handle 1.65V. These intermediaries buffer the voltage difference, allowing standard devices to operate safely in a 1.8V I/O environment.
Data Source
AI summary
A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.