Level Shifting Circuit With Current Mirror Pulse Assist

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Solution Overview

Problem

Existing level shifting circuits face issues with prolonged output voltage due to parasitic capacitance in block transistors, leading to potential gate oxide damage and operational delays.

Innovation Solution

A level shifting circuit design that includes a current provision unit with a current mirror structure and a block module to prevent gate oxide breakdown, using a pulse signal to provide additional current and overlap output currents, thereby shortening the prolonged portion of the output voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a block transistor is used to protect the gate oxide, then the gate oxide breakdown is prevented, but the output voltage is prolonged due to parasitic capacitance

Engineering Contradiction:
Improvegate oxide protectionVSAvoidoutput voltage duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the protective function from the main signal path by using a separate block transistor that is activated only when needed. The block transistor is connected in parallel with the main transistor and is controlled by a separate control signal, allowing it to provide protection without being continuously in the signal path. This extraction approach allows the protective function to be separated from the signal transmission path, reducing the impact of parasitic capacitance on the output voltage duration.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements preliminary action by pre-positioning the block transistor in a standby state with its control signal prepared in advance. When a breakdown condition is detected or anticipated, the block transistor can be activated immediately to protect the gate oxide. The control circuit monitors the voltage conditions and prepares the block transistor for activation, ensuring that protection is available before damage occurs while minimizing the time the block transistor affects the normal signal path.

Inventive Principle:
Principle #10Preliminary action

2Strength

If the gate-source voltage exceeds the breakdown voltage, then the transistor can handle higher voltages, but the gate oxide becomes damaged

Engineering Contradiction:
Improvevoltage handling capabilityVSAvoidgate oxide integrity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent introduces an intermediary block transistor that acts as a mediator between the high-voltage input signal and the main transistor. The block transistor is positioned in parallel with the main transistor and is controlled to activate when the gate-source voltage approaches the breakdown voltage. This intermediary device provides a alternative current path that protects the main transistor's gate oxide from excessive voltage stress while still allowing the circuit to handle high voltages through the block transistor.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements beforehand cushioning by providing a protective block transistor that is activated in advance before the gate oxide can be damaged. The control circuit monitors the voltage conditions and activates the block transistor when the gate-source voltage approaches the breakdown threshold, creating a protective cushion that prevents direct exposure of the gate oxide to damaging voltages. This prior protection mechanism ensures that the main transistor is shielded before damage can occur.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively shortens the prolonged output voltage, enhancing the speed and protecting the gate oxide of transistors by preventing voltage exceedance, thus improving the operational efficiency of the level shifting circuit.

Implementation Method 1

a delay may be generated by a parasitic capacitance of the block transistor, which may unnecessarily prolong the output voltage

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

The current provision unit may include a current output module having a current mirror structure

Methodology Applied
Scientific EffectCurrent mirror effect:

Data Source

PatentUS9825634B2Level shifting circuit and method for the same
Publication Date: 2017.11.21 MAGNACHIP SEMICON LTD
  • US9825634B2 patent drawing
  • US9825634B2 patent drawing
  • US9825634B2 patent drawing

AI summary

A level shifting circuit includes a transistor output unit that receives a first power supply signal and convert the first power supply signal to a second power supply signal having a different level from the first power supply signal and a current provision unit that provides a current to an output terminal of the transistor output unit when the first power supply signal of the transistor output unit is inputted to shorten a prolonged portion of the second power supply signal. Therefore, the level shifting circuit may provide an additional current to the output terminal of the transistor output unit to shorten a prolonged portion of the output voltage.