Level-Shiftless Transmitter Driver Circuit for High-Bandwidth SERDES
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Solution Overview
Problem
Conventional high-speed SERDES transmitters are current-consuming and require driver circuits with high bandwidth and high launch amplitude, often necessitating level shifters that increase power consumption and limit bandwidth due to parasitic capacitance and large layout areas.
Innovation Solution
A level-shiftless transmitter driver circuit utilizing PMOS and NMOS devices with resistors and a sub-circuit to operate in a lower voltage domain, eliminating the need for level shifters and reducing parasitic capacitance, thereby enhancing bandwidth and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If level shifters are used to achieve high launch amplitude, then the output signal amplitude is improved, but the bandwidth is limited due to parasitic capacitance and the power consumption increases
Solution Approach 1:
The patent removes level shifters from the transmitter driver circuit, extracting the problematic component that caused bandwidth limitation through parasitic capacitance. The circuit achieves high launch amplitude directly through optimized PMOS/NMOS device configuration and voltage domain design without requiring separate level shifting stages.
Solution Approach 2:
The patent changes the voltage domain parameters by operating the driver circuit in a lower voltage domain (1.0V) compared to conventional high voltage domain (1.2V) designs. This parameter change enables direct achievement of high launch amplitude without level shifters, improving bandwidth while maintaining signal strength through optimized device sizing and configuration.
2Adaptability or versatility
If level shifters are used to connect different voltage domains, then voltage level compatibility is improved, but the layout area increases due to large transistor sizes required
Solution Approach 1:
The patent extracts and removes level shifter components from the circuit design, eliminating the need for large transistor sizes associated with level shifting operations. The circuit achieves voltage domain compatibility directly through its core driver architecture, significantly reducing the required layout area.
3Strength
If conventional high voltage domain (1.2V) is used, then the launch amplitude is sufficient, but the current consumption increases
Solution Approach 1:
The patent changes the operating voltage parameter from conventional 1.2V high voltage domain to 1.0V lower voltage domain. Through optimized PMOS/NMOS device configuration and sizing, the circuit maintains sufficient launch amplitude at the lower voltage while achieving reduced current consumption, directly resolving the trade-off between amplitude and power usage.
4Strength
If driver circuit operates in high voltage domain, then the signal strength is improved, but the bandwidth is reduced due to parasitic capacitance
Solution Approach 1:
The patent changes the operating voltage parameter to a lower voltage domain (1.0V), which inherently reduces parasitic capacitance effects and enables higher bandwidth operation. The circuit maintains adequate signal strength through optimized device configuration rather than relying on high voltage, thus achieving both good signal quality and wide bandwidth simultaneously.
Data Source
AI summary
A level-shiftless transmitter includes a transmitter driver circuit. The transmitter driver circuit includes a first PMOS device, a second PMOS device, a first NMOS device, a second NMOS device, and a sub-circuit. The sources of the first and second PMOS devices are electrically coupled with each other. The gates of the first PMOS and the first NMOS devices are electrically coupled with each other. The gates of the second PMOS and the second NMOS devices are electrically coupled with each other. The sub-circuit is electrically coupled with a voltage domain to provide a voltage lower than the voltage domain to the sources of the first and second PMOS devices.