Level Switching Circuit for Rail-to-Rail Disable on Power Failure
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Solution Overview
Problem
Existing logic chips used to control Rail-to-Rail enabling signals often fail to operate when power is lost, leading to errors in signal control due to unstable states of PMOS transistors, which affects the accuracy of enabling control signals for equipment.
Innovation Solution
A level switching circuit is designed to receive input signals and output enabling or disabling signals based on high or low levels, with a PMOS transistor configured to be on or off according to signal levels and a resistor to output enabling or disabling signals, ensuring accurate control even during power supply failures by switching to a disabling signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing logic chips are used to control Rail-to-Rail enabling signal, then the circuit can operate normally during power supply, but the circuit stops operating and produces errors when power is lost
Solution Approach 1:
The patent introduces a level switching circuit as an intermediary component between the power supply and the enabling signal control. This circuit includes a PMOS transistor and resistor that act as mediators to detect power supply status and automatically switch signal levels. When power is normal, it outputs the enabling signal; when power fails, it switches to output a disabling signal, thus resolving the contradiction between normal operation and power failure response.
Solution Approach 2:
The level switching circuit is configured to preliminarily detect the power supply voltage status before the main control logic operates. By using the PMOS transistor and resistor network to pre-establish the signal level based on power status, the system proactively prepares the correct signal state (enabling or disabling) before any potential errors can occur, ensuring reliable operation across both normal and failure conditions.
2Ease of operation
If PMOS transistors are used in the control circuit, then enabling control can be achieved, but the transistors enter unstable states during power failure causing signal errors
Solution Approach 1:
The patent changes the operating parameters of the PMOS transistor by configuring it in a level switching arrangement with a resistor connected to a reference voltage. This parameter configuration ensures that the transistor operates in stable regions: when power is normal, the gate-source voltage keeps the transistor in a stable on/off state; when power fails, the voltage collapse naturally drives the transistor to a stable cutoff state, eliminating unstable intermediate states.
3Device complexity
If a simple enabling control circuit is used, then the circuit design is straightforward, but it cannot distinguish between normal operation and power failure conditions
Solution Approach 1:
The level switching circuit performs multiple functions simultaneously: it acts as a signal level translator, a power failure detector, and an automatic switch controller. The same PMOS transistor and resistor configuration that enables the enabling control function also inherently detects power status and generates the appropriate disabling signal, achieving multi-functionality without significantly increasing circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures accurate enabling control signals are maintained by outputting a disabling signal during power failures, preventing errors and ensuring equipment operation, even when power supply voltage is normal or failed.
Implementation Method 1
Positive Channel Metal-Oxide-Semiconductor Field-Effect Transistors (PMOS) M1, M3, M5, M7, and M8... The PMOS M1 has a substrate and a source both connected to a power supply pwrin, a gate receiving an input signal in, and a drain connected to a drain of the NMOS M2
Implementation Method 2
The resistor R1 is connected, at one end, to the drain of the PMOS M3 and to a gate of the NMOS M6... The resistor R2 is connected, at one end, to the drain of the PMOS M5 and to the gate of the NMOS M4
Data Source
AI summary
This document discusses, among other things, methods for controlling a Rail-to-Rail enabling signal, including providing a first signal of an input signal of a control circuit to a level switching circuit, performing, by the level switching circuit, enabling control according to a high level and a low level of the first signal, and outputting, by the level switching circuit, a disabling signal in case of a failure of a power supply coupled to the level switching circuit. The document also discusses a circuit for controlling a Rail-to-Rail enabling signal and a level switching circuit configured to output a disabling signal properly to provide an accurate enabling control signal for equipment operated under control of an enabling control in case of the failure of the power supply.