Voltage Level Translator Bypass for Equal-Supply Signal Paths
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Solution Overview
Problem
Conventional voltage level translators consume power and introduce delay even when the supply voltages of different domains are equal, as they remain active and perform unnecessary voltage translation.
Innovation Solution
A power-efficient voltage level translator circuit that includes a bypass mode to bypass the translator when supply voltages are equal, and a power-down circuit to shut down the translator in this mode, avoiding unnecessary power consumption and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage level translator remains active to translate signals between voltage domains, then voltage level translation is ensured, but power consumption increases and delay is introduced even when supply voltages are equal
Solution Approach 1:
The voltage level translator is designed with dynamic control capability, allowing it to switch between active translation mode and bypass mode based on real-time voltage domain comparisons. The controller dynamically adjusts the translator's operational state, enabling it to be active only when voltage levels differ, thereby reducing unnecessary power consumption while maintaining translation capability when needed.
Solution Approach 2:
The system monitors and compares voltage parameters (VDD1 and VDD2) of different voltage domains and changes the operational parameter of the voltage level translator based on this comparison. When voltages are equal, the translator is disabled or bypassed; when voltages differ, the translator is activated. This parameter-based control resolves the contradiction by adapting the translator's state to actual voltage conditions.
2Reliability
If the voltage level translator remains active to translate signals between voltage domains, then voltage level translation is ensured, but signal delay increases even when supply voltages are equal
Solution Approach 1:
The voltage level translator incorporates dynamic switching capability that responds to voltage domain equality conditions. When VDD1 equals VDD2, the system dynamically routes signals through a bypass path, eliminating the translator from the signal path and thus removing its associated delay. This dynamic adaptation ensures translation reliability only when actually needed, minimizing signal delay in all other cases.
Solution Approach 2:
The signal transmission path is segmented into two possible routes: one through the voltage level translator and another bypass path. The controller selectively activates one route based on voltage comparison results. This segmentation allows the system to choose the direct bypass path (zero delay) when voltages are equal, while maintaining the translation path available when voltage level translation is required.
3Use of energy by moving object
If the voltage level translator is bypassed when supply voltages are equal, then power consumption is reduced and delay is eliminated, but voltage level translation capability is lost when voltages are equal
Solution Approach 1:
The system implements a feedback mechanism where the controller continuously monitors the voltage levels VDD1 and VDD2 of different voltage domains. Based on this feedback information, the controller determines whether to activate the voltage level translator or enable the bypass path. This feedback-driven control ensures that the translator is activated only when voltage levels differ, maintaining translation capability precisely when needed while enabling power-saving bypass mode when voltages are equal.
Solution Approach 2:
The voltage level translation system performs self-assessment by comparing its own operating conditions (voltage domain equality) and automatically adjusts its operational state accordingly. The controller within the system independently determines whether translation is needed and configures the signal path without external intervention, enabling the system to serve itself by switching between translation and bypass modes based on its own voltage conditions.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C
AI summary
Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage (vdd1) of the first voltage domain and a second supply voltage (vdd2) of the second voltage domain are different, the voltage level translator (250) translates an input signal (a, a_n) in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit (252) is configured to bypass the voltage level translator (250) and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit (275) is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.