Level-Up Shifter Circuit for Duty-Cycle Fidelity and Low Static Power
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Solution Overview
Problem
Conventional level-up shifter circuits experience significant static power dissipation and leakage current when handling signals across power domains with a voltage difference, particularly at high speeds, which is undesirable for modern IC design due to increased power dissipation and reduced duty cycle fidelity.
Innovation Solution
A level-up shifter circuit design that minimizes static power dissipation by using a configuration of transistors and buffers to eliminate DC current paths, maintaining duty cycle fidelity across varying process, voltage, and temperature conditions, even with significant power domain differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional level-up shifter is used to transfer signals from core power domain to IO power domain, then signal level shifting is achieved, but significant static power dissipation and leakage current occur
Solution Approach 1:
The circuit uses dynamic control of transistor gates to enable/disable current paths based on signal transitions. The level-up shifter dynamically switches between different conduction states using the input signal and its complement to control the pass transistors, ensuring current flows only when necessary for signal transmission.
Solution Approach 2:
The circuit operates in periodic cycles where transistors are turned on and off based on the clocked or pulsed nature of digital signals. The pass transistors conduct current only during the active periods when signal transitions occur, rather than maintaining continuous DC current paths between power domains.
2Speed
If a level-up shifter handles rail to rail signal levels for full-swing GHz high speed signals, then signal speed is improved, but duty cycle fidelity is compromised
Solution Approach 1:
The circuit introduces intermediate buffering stages and controlled impedance paths that mediate between the input and output signal domains. The pass transistors act as controlled intermediaries that transfer signal edges while maintaining their temporal characteristics, and the output buffer restores the signal to full swing without distorting the duty cycle.
Solution Approach 2:
The circuit dynamically adjusts transistor channel resistance and signal voltage levels during transmission. By controlling the gate voltages of pass transistors and using buffered stages with optimized load conditions, the circuit maintains signal integrity and duty cycle fidelity across the voltage translation between power domains.
3Adaptability or versatility
If the difference between core and IO supply grows larger to provide wider power supply range, then adaptability is improved, but short-circuit currents increase
Solution Approach 1:
The circuit dynamically controls the resistance of pass transistors based on the instantaneous signal voltage and power domain voltage difference. When the voltage difference between core and IO domains is large, the transistor gates are controlled to ensure optimal conduction without creating uncontrolled current paths, adapting to the specific voltage conditions.
Solution Approach 2:
The circuit uses the input signal and its complement as feedback control signals for the pass transistor gates. This feedback mechanism ensures that current paths are only enabled when the input signal indicates a valid transition, preventing short-circuit currents even when large voltage differences exist between power domains.
Data Source
AI summary
A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.