Leveling Dielectric Fill for Semiconductor Contact Topography
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Solution Overview
Problem
In semiconductor devices with critical dimensions of 50 nm and less, significant contact failures occur due to pronounced surface topography and material loss in trench isolation regions, leading to short circuits and conductive paths between adjacent active regions, which hinder further scaling and increase yield loss.
Innovation Solution
A dielectric fill material is applied above and laterally adjacent to transistor elements before forming contact elements, leveling the surface topography and providing a stable base for contact formation, thereby reducing the risk of misalignment and deposition-related voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If critical dimensions are reduced to increase integration density, then integration density is improved, but contact failures increase due to pronounced surface topography and material loss
Solution Approach 1:
A dielectric fill material is deposited in advance to fill trenches and level the surface topography before contact hole formation. This preliminary action creates a flat surface that prevents misalignment and deposition voids, thereby reducing contact failures while maintaining high integration density
Solution Approach 2:
The dielectric fill material acts as an intermediary layer between the trench isolation structure and the contact holes. It mediates the surface topography issue by providing a flat deposition surface, preventing direct contact between metal and irregular surfaces that would cause short circuits
2Reliability
If trench isolation regions are formed to separate active regions, then device isolation is improved, but surface topography becomes pronounced causing misalignment and short circuits
Solution Approach 1:
The dielectric fill material is deposited preliminarily to fill the trenches created by isolation regions and level the surface. This creates a flat surface for subsequent contact hole formation, eliminating misalignment issues while preserving the isolation function
Solution Approach 2:
The dielectric fill material is selectively applied to trench regions with pronounced topography while leaving other areas unchanged. This local modification levels only the problematic areas, maintaining isolation where needed while improving alignment precision where contacts are formed
3Device complexity
If conventional processes are used without dielectric fill, then process complexity is reduced, but deposition voids and short circuits occur
Solution Approach 1:
The dielectric fill material serves as an intermediary layer that prevents direct deposition of metal onto irregular surfaces. This intermediary layer eliminates void formation and prevents short circuits between adjacent active regions, with the added complexity being offset by the elimination of defect-related rework
Data Source
AI summary
The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.