1T2C Memory Cell Arrangement With Lever Capacitor
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Solution Overview
Problem
Current memory cell technologies face challenges in efficiently writing and reading data without causing disturbances, particularly in AND architectures with standard 1T1C ferroelectric field-effect transistors, which suffer from high power consumption and read disturb issues due to reverse junction leakages and non-linear capacitance ratios.
Innovation Solution
The implementation of a 1T2C memory cell arrangement with a ferroelectric capacitor and a lever capacitor structure, where the lever capacitor modifies voltage distributions to reduce write voltages and prevent read disturb, allowing for efficient writing and reading by tuning the capacitance divider during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If standard 1T1C ferroelectric memory cell is used, then device complexity is reduced, but read disturb and reverse junction leakages occur due to non-linear capacitance ratios
Solution Approach 1:
A lever capacitor is introduced as an intermediary component between the ferroelectric capacitor and the transistor gate. This lever capacitor acts as a mediator that transforms the voltage distribution, enabling linear capacitance ratios and preventing read disturb effects while maintaining control over the transistor gate.
Solution Approach 2:
The patent changes the capacitance parameter relationship by introducing the lever capacitor to achieve linear capacitance ratios. By adjusting the capacitance values of the lever capacitor relative to the ferroelectric capacitor, the system transitions from non-linear to linear capacitance ratios, eliminating reverse junction leakages and read disturb issues.
2Reliability
If high write voltages are applied to ensure reliable writing, then writing reliability is improved, but power consumption increases
Solution Approach 1:
The lever capacitor modifies the voltage distribution parameters during write operations. By changing the capacitance ratio parameters, the system achieves reliable writing at reduced voltage levels, thereby lowering power consumption while maintaining writing reliability.
Solution Approach 2:
The lever capacitor serves as a voltage transformation intermediary that distributes write voltages more efficiently. It transforms the voltage applied to the ferroelectric capacitor, enabling reliable data writing with reduced overall voltage requirements and consequently lower power consumption.
3Speed
If fast reading is achieved by applying high voltages, then reading speed is improved, but read disturb effects increase
Solution Approach 1:
The lever capacitor acts as a voltage distribution intermediary during read operations. It transforms and distributes the read voltage in a controlled manner, enabling fast reading speeds while preventing excessive voltage from causing read disturb effects on adjacent memory cells.
Solution Approach 2:
By adjusting the capacitance parameters of the lever capacitor, the voltage distribution during reading is optimized. This parameter change enables achieving fast reading speeds through controlled voltage application while preventing read disturb by maintaining voltage within safe operational limits.
4Ease of manufacture
If conventional memory cell design is used, then manufacturing process is simplified, but control over field-effect transistor is insufficient for long channel transistors
Solution Approach 1:
The lever capacitor is introduced as an intermediary control element between the ferroelectric capacitor and the transistor gate. This additional control mechanism provides enhanced control over long channel transistors, enabling proper operation while maintaining compatibility with conventional manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces write voltages, minimizes read disturb, and avoids reverse junction leakages, enabling faster and more reliable data operations while maintaining control over the field-effect transistor, even for long channel transistors.
Implementation Method 1
The implementation of a 1T2C memory cell arrangement with a ferroelectric capacitor and a lever capacitor structure, where the lever capacitor modifies voltage distributions to reduce write voltages and prevent read disturb, allowing for efficient writing and reading by tuning the capacitance divider during operations.
Data Source
AI summary
A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.