LFSR CRC Initialization for Clean-Sector Error Detection
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Solution Overview
Problem
Existing memory systems face challenges in effectively detecting errors during data transmission processes, particularly in identifying errors in clean sectors where all bit values are '1', which can lead to incorrect CRC parity information and compromised data integrity.
Innovation Solution
A method involving a linear feedback shift register (LFSR) circuit initialized with specific register values to generate CRC parity information, ensuring that when input data is all '1', the CRC parity information also matches the pattern, thereby preventing errors during copy-back operations and data integrity checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CRC initialization is used, then the CRC operation can be performed, but errors occur in clean sectors where all bit values are '1' leading to incorrect CRC parity information
Solution Approach 1:
The patent changes the initialization parameter of the LFSR circuit from conventional values (all '0' or specific patterns) to a non-conventional initial value that ensures when input data is all '1', the CRC parity information also matches the all-'1' pattern. This parameter change resolves the contradiction by making the CRC operation reliable for clean sectors while maintaining accuracy for all data patterns.
2Reliability
If the LFSR circuit is initialized with conventional values, then the circuit structure remains simple, but false positives occur in error detection
Solution Approach 1:
The patent applies parameter change by modifying the LFSR initial value parameter to a specifically designed non-conventional value. This single parameter modification improves error detection accuracy by preventing false positives in clean sectors, while the implementation complexity remains minimal as it only requires setting an initial register value rather than adding complex circuitry.
Data Source
AI summary
A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.