Linear Feedback Shift Register Configuration for Cryptographic Memory Optimization
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Solution Overview
Problem
Existing methods for implementing high-dimensional linear transformations in cryptographic systems are inefficient in resource usage and unable to optimize performance and memory requirements, leading to increased processor cycles and memory needs.
Innovation Solution
The method involves generating Galois-type or Fibonacci-type Linear Feedback Shift Registers (LFSRs) with specific configurations and parameters to perform high-dimensional linear transformations, allowing for the selection of optimal performance and memory usage by determining the number of cycles required based on processor word size and available memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If low-dimensional linear transformations are used, then implementation complexity is reduced, but security level is insufficient requiring additional transformations and more processor cycles
Solution Approach 1:
The patent transitions from low-dimensional linear transformations to high-dimensional linear transformations by using LFSRs with a large number of stages (e.g., 128 stages for AES-128). This dimensional expansion allows the single transformation to process the entire block simultaneously, eliminating the need for additional transformations while maintaining security.
2Reliability
If high-dimensional linear transformations are implemented using conventional methods, then security level is improved, but processor cycles and memory requirements increase
Solution Approach 1:
The patent changes the parameters of the LFSR system by allowing flexible selection of the number of stages based on the block size. For example, using 128 stages for AES-128 (16 bytes × 8 bits) optimizes the balance between security and performance. This parameter optimization reduces processor cycles while maintaining high security level.
Solution Approach 2:
The patent extracts and eliminates redundant additional linear transformation steps that are required in conventional low-dimensional approaches. By using high-dimensional LFSRs, the entire block transformation is completed in a single operation, removing the need for separate ShiftRows or similar functions, thus improving performance.
3Ease of manufacture
If LFSR parameters are fixed, then implementation is simplified, but adaptability to different computing platforms is reduced
Solution Approach 1:
The patent introduces dynamic configurability to the LFSR system by allowing the number of stages to be adjusted according to the specific computing platform and block size requirements. The method provides flexible parameter selection including the number of stages, feedback polynomial, and initial state, enabling adaptation to different hardware and software environments while maintaining a consistent implementation framework.
Data Source
AI summary
The invention relates to the field of computer engineering and cryptography and, in particular, to methods for implementing linear transformations that operate with a specified speed and require minimum amount of memory, for further usage in devices for cryptographic protection of data. The technical result enables the selection of interrelated parameters (performance and required amount of memory) for a particular computing system when implementing a high-dimensional linear transformation. The use of the present method allows for a reduction of the amount of consumed memory at a given word size of processors employed. To this end, based on a specified linear transformation, a modified linear shift register of Galois-type or Fibonacci-type is generated according to the rules provided in the disclosed method, and the usage thereof enables to obtain the indicated technical result.