LFSR Memory Traffic Generator for Full-Bandwidth Subsystem Validation
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Solution Overview
Problem
Existing memory subsystem validation methods require many active cores and a healthy fabric to drive full memory bandwidth, which is time-consuming and risks delaying product release schedules, especially in Systems on Chip (SOC) with compute and IO dies.
Innovation Solution
A low-cost hardware engine using Linear Feedback Shift Registers (LFSRs) generates pseudo-random sequences to simulate real-world traffic patterns, enabling full memory bandwidth testing independent of the SOC, and replicating workload and OS behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If many active cores and healthy fabric are used to drive full memory bandwidth, then memory subsystem validation is achieved, but validation time increases and product release schedules are delayed
Solution Approach 1:
The patent uses a hardware traffic generator to create synthetic memory traffic patterns that copy and simulate real-world workload behavior. Instead of relying on multiple active CPU cores to generate test traffic, the traffic generator produces equivalent memory access patterns independently, enabling full bandwidth validation without requiring numerous processor cores or waiting for fabric health checks.
2Reliability
If full memory bandwidth is driven across all channels for validation, then comprehensive memory testing is achieved, but the requirement for many active cores increases device complexity
Solution Approach 1:
The patent extracts the traffic generation function from the CPU cores and places it in a dedicated hardware traffic generator. This separation allows memory bandwidth validation to proceed without requiring multiple active processor cores, as the traffic generator independently provides the necessary test traffic to exercise all memory channels at full bandwidth.
Solution Approach 2:
The hardware traffic generator acts as an intermediary between the test system and the memory subsystem. It generates synthetic traffic patterns that mimic real workloads and injects them directly into the memory controller, eliminating the need for CPU cores to serve as traffic sources and simplifying the overall test configuration.
3Reliability
If disaggregated memory die validation is performed under high bandwidth conditions, then standalone memory die testing is achieved, but the requirement for high bandwidth driving capability increases power constraints
Solution Approach 1:
The traffic generator creates synthetic memory traffic that copies real workload patterns, enabling standalone memory die validation without requiring actual processor cores. This approach achieves high bandwidth testing conditions while using a dedicated hardware device optimized for traffic generation rather than general-purpose computing, thereby managing power consumption more efficiently.
Data Source
AI summary
A device includes an injection determiner that includes a linear-feedback shift register (LFSR), configured to generate an LFSR-output for control of a probability of sending a read command or a write command; wherein the injection determiner is configured to compare the LFSR-output to a range of prospective LFSR-outputs; send a command to read from a memory or a command to write to a memory if the LFSR-output is within the range, and send no command to read from the memory and no command to write to the memory if the LFSR-output is outside of the range.