LFSR Encryption for Multi-Processor Cache Security
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Solution Overview
Problem
In multi-processor systems with shared cache memory, existing encryption techniques are inadequate for protecting processor instructions and data from snooping and tampering, as they require significant computational overhead and are not sufficiently robust to prevent unauthorized access.
Innovation Solution
A multi-processor system employing pseudo-random numbers generated by Linear Feedback Shift Registers (LFSRs) for encrypting and decrypting instructions and data between processors and shared memory, using logic to translate instructions and data with pseudo-random keys, ensuring minimal overhead and transparent encoding/decoding within individual processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based encryption techniques or traditional encryption methods are used to protect processor instructions and data, then security is improved, but computational overhead increases significantly
Solution Approach 1:
The patent replaces software-based encryption mechanisms with hardware-based LFSR circuits integrated into the processor. This substitution of mechanical/hardware systems for software algorithms dramatically reduces computational overhead while maintaining security, as the LFSR operations are performed in parallel hardware rather than sequential software instructions.
Solution Approach 2:
The patent uses LFSR-generated pseudo-random sequences as cryptographic keys, creating a copy of the encryption mechanism that can be efficiently reproduced and distributed. The LFSR polynomials and initial states serve as compact representations that generate long pseudo-random key sequences, reducing the storage and transmission overhead compared to traditional key management.
2Productivity
If LFSR-based pseudo-random encryption is used, then computational overhead is reduced, but encryption robustness may be compromised
Solution Approach 1:
The patent merges multiple LFSR circuits with different polynomials and initial states to generate composite encryption keys. By combining the outputs of multiple LFSRs through XOR operations or other combination functions, the system achieves encryption robustness comparable to traditional methods while maintaining the low computational overhead of hardware-based generation.
Solution Approach 2:
The encryption system uses composite cryptographic keys formed by combining multiple LFSR-generated sequences. This composite approach creates a multi-layered encryption mechanism where the security strength is the product of individual LFSR strengths, achieving robustness equivalent to traditional encryption while retaining hardware efficiency.
3Productivity
If multiple processors share cache memory, then system productivity is improved, but security is worsened due to snooping capabilities
Solution Approach 1:
The patent implements local encryption where each processor core has its own LFSR circuit that generates unique pseudo-random keys for encrypting and decrypting its own instructions and data. This local quality approach ensures that even though cache is shared, each processor operates with its own security domain, preventing cross-processor snooping attacks while maintaining shared cache productivity.
Solution Approach 2:
The shared cache memory is effectively segmented into secure zones by the LFSR-based encryption. Each processor's encrypted data and instructions are isolated in their own cryptographic space within the shared cache, preventing other processors from accessing or snooping on another processor's data despite physical sharing of the cache memory structure.
Data Source
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Figure 1b
Figure 2a~2b
AI summary
Techniques and logic are presented for encrypting and decrypting programs and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual. LI. cache memory or between a processor's instruction and execution unit and their respective LI caches. The logic may include one or more linear feedback shift registers (L.FSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used tor test purposes.