Spectral Shaping of Spread Spectrum Clocks via LFSR Post-Processing

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Solution Overview

Problem

Switch mode DC-to-DC converters generate undesirable noise spurs at the switching frequency, which interfere with electronic device performance and are not effectively mitigated by existing technologies.

Innovation Solution

A linear feedback shift register (LFSR) generates a pseudo-random sequence of timebase control word values, and a spectral shaping post-processing component adjusts mid-range values to spread the switching noise across a range of frequencies, reducing the amplitude of noise at any single frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If spread spectrum clocking is used to reduce switching noise, then noise amplitude at single frequency is reduced, but noise energy is redistributed across frequency spectrum

Engineering Contradiction:
Improveswitching noise amplitudeVSAvoidnoise energy distribution
Core Design Contradiction:
Object-affected harmful factorsVSLoss of energy

Solution Approach 1:

The patent segments the concentrated noise energy at a single switching frequency into distributed noise across multiple frequencies. By using a linear feedback shift register (LFSR) to modulate the switching frequency, the noise spectrum is divided and spread across a range of frequencies, reducing the amplitude at any individual frequency point while maintaining total noise energy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic frequency modulation of the switching signal using an LFSR-generated pseudo-random sequence. The switching frequency varies dynamically according to the LFSR output states, transforming a static single-frequency noise source into a dynamic multi-frequency noise distribution, thereby reducing peak noise amplitude.

Inventive Principle:
Principle #15Dynamics

2Object-affected harmful factors

If LFSR-based frequency spreading is implemented, then mid-range noise is minimized, but device complexity increases

Engineering Contradiction:
Improvemid-range noiseVSAvoidtimebase generator complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent employs a linear feedback shift register (LFSR) that uses feedback connections to generate a pseudo-random sequence. The feedback mechanism allows the LFSR to produce a deterministic yet unpredictable sequence of frequency modulation values, achieving noise spreading without requiring external random number generators or complex control logic.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the frequency parameter of the switching signal dynamically based on LFSR output states. By mapping different LFSR states to different switching frequencies, the system achieves spectral spreading through parameter modulation, minimizing mid-range noise while using a relatively simple digital logic structure.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11601053B2Spectral shaping of spread spectrum clocks/frequencies through post processing
Publication Date: 2023.03.07 TEXAS INSTRUMENTS INC
  • US11601053B2 patent drawing
  • US11601053B2 patent drawing
  • US11601053B2 patent drawing

AI summary

An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.