LFSR State-Vector Emulation for Multi-Bit Clock Shifting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional implementations of scrambling-code generators and CRC generators using linear-feedback shift registers (LFSRs) require one clock cycle per bit, limiting data processing speed.
Innovation Solution
Emulating LFSRs using a state vector that can be multiplied by a time shift matrix to perform multiple steps in a single clock cycle, reducing the need for extensive calculations and storage by focusing only on the impact of the LFSR content and input sections on the output sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LFSR is implemented in hardware as traditional linear-feedback shift register, then the implementation is simple and reliable, but the processing speed is limited to one clock cycle per bit
Solution Approach 1:
The patent replaces the traditional hardware LFSR mechanical shifting operation with a mathematical matrix multiplication operation. Instead of physically shifting bits one position at a time through flip-flops and XOR gates, the invention uses matrix multiplication over GF(2) to compute the next state directly, achieving parallel processing of multiple bits in a single clock cycle.
Solution Approach 2:
The invention changes the fundamental parameter of operation from sequential bit-by-bit processing to parallel multi-bit processing. By raising the transfer matrix A to the nth power (An), the system can advance the LFSR state by n positions in a single operation, fundamentally changing the speed parameter while maintaining the same mathematical structure.
2Productivity
If LFSR is emulated using full state vector multiplication by time shift matrix, then multiple steps can be performed in single clock cycle, but the calculation complexity and storage requirements increase
Solution Approach 1:
The patent extracts and processes only the relevant portions of the state vector that actually influence the output. By identifying that only certain sections of the state vector (those describing LFSR content and input sections) have impact on the output sections, the invention performs multiplication only for those specific parts, eliminating unnecessary calculations involving other state vector sections.
Solution Approach 2:
The state vector is segmented into distinct sections: input sections, LFSR content sections, and output sections. This segmentation allows the system to selectively process only the impactful sections (input and LFSR content) when multiplying by the time shift matrix, rather than performing full-state multiplication, thereby reducing computational complexity while maintaining productivity gains.
3Reliability
If state vector sections are dimensioned to accommodate inputs and outputs at different times, then the time shift emulation is accurate, but the storage requirements increase
Solution Approach 1:
The patent applies partial action by dimensioning the state vector sections only to the extent necessary to accommodate the specific time shift requirements. Rather than providing full storage for all possible intermediate states, the invention sizes the input and output sections precisely to match the needs of the time shift matrix operation, avoiding excessive storage allocation while maintaining emulation accuracy.
Data Source
AI summary
Apparatus for emulating the operation of an LFSR having at least one of one or more inputs and one or more outputs, wherein the state of the LFSR can be described by a state vector having sections describing the input or inputs, if any, of the LFSR, the contents of the LFSR and the output or outputs, if any, of the LFSR, wherein the state vector can be multiplied by a time shift matrix to time shift the state specified by the vector and wherein the apparatus comprises means for multiplying a first instance of the state vector by the matrix to produce a second instance of the state vector that is time shifted relative to the first instance and wherein one or both of the input and output sections of the state vector are dimensioned to accommodate, respectively, inputs that arrive at different times during the time shift specified by the matrix and outputs that are produced at different times during the time shift.