Land Grid Array Interposer for High-Density Semiconductor Packaging

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Solution Overview

Problem

Conventional semiconductor device packaging techniques face challenges with ever-smaller semiconductor dice and closely pitched bond pads, leading to difficulties in wire bonding, overcrowding, and limited device density, as well as a lack of repairability and compatibility with dissimilar components.

Innovation Solution

A land grid array package with an interposer substrate and a two-dimensional pad array that allows for wire bonding to terminal pads, enabling connection to both land grid array lands and a two-dimensional pad array for enhanced testing and repair, facilitating high device density and multi-die assemblies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If lead frame-based packaging techniques are used with wire bonds to connect bond pads to lead fingers, then electrical connection is achieved, but it becomes difficult or impossible when bond pad size and pitch decrease due to semiconductor shrinks

Engineering Contradiction:
Improvebond pad size and pitchVSAvoidwire bonding difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent introduces an interposer substrate as an intermediary component between the semiconductor die and the lead frame. This interposer provides a larger, more accessible pad array that can be wire bonded to, eliminating the need to directly wire bond to the small, closely-spaced bond pads on the die itself. The interposer acts as a mediator that decouples the small die pitch from the larger wire bond pitch requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If bond pads are arranged along a central axis in LOC packages, then connection is possible, but lead fingers become overcrowded or wire bonds become overly long risking breakage or shorting

Engineering Contradiction:
Improveconnection capabilityVSAvoidwire bond reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent transitions from the conventional one-dimensional central axis arrangement of bond pads in LOC packages to a two-dimensional pad array arrangement on the interposer substrate. This dimensional change allows pads to be distributed across a larger area in both X and Y directions, reducing overcrowding of lead fingers and shortening wire bond lengths by providing multiple access points around the die perimeter rather than only from the center.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If conventional packages are used, then basic packaging is achieved, but high device density and multi-die assembly yields are not facilitated

Engineering Contradiction:
Improvedevice densityVSAvoidpackage structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The interposer substrate serves multiple functions simultaneously: it provides electrical interconnection between dies, offers a platform for wire bonding, enables high-density packaging arrangements, and facilitates testing access. This multi-functional design allows a single component to address multiple packaging challenges, enabling high device density without proportionally increasing overall package complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of repair

If conventional packages are used, then assembly is complete, but repair capability before or after assembly is not provided

Engineering Contradiction:
Improverepair capabilityVSAvoidpackage structure
Core Design Contradiction:
Ease of repairVSDevice complexity

Solution Approach 1:

The patent segments the packaging system into distinct, independently accessible components: the semiconductor die, the interposer substrate, and the lead frame or carrier. This segmentation allows the interposer to be separated from the die and lead frame, enabling repair or replacement operations on individual components without requiring disassembly of the entire package. The interposer's external pad array provides access points for testing and repair before final assembly.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP1929540B1Land grid array semiconductor device package and fabrication method thereof
Publication Date: 2014.07.16 MICRON TECHNOLOGY INC
  • EP1929540B1 patent drawingFigure 1~2A
  • EP1929540B1 patent drawingFigure 3
  • EP1929540B1 patent drawingFigure 4

AI summary

A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.