Library Cell Exclusion for Delay Optimization
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Solution Overview
Problem
Conventional circuit synthesis approaches rely on iterative trial-and-error methods with discretized delay models, leading to inefficiencies and poor quality results, especially for large designs with many timing constraints, due to the inaccuracy of linear delay models.
Innovation Solution
The use of numerical delay models for optimizing circuit designs by excluding library cells with specific logical and parasitic delay values that exceed certain thresholds, allowing for iterative refinement of generic values to improve model accuracy and reduce timing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error optimization is used to size cells, then timing constraints can be checked and violated cell sizes rejected, but the process takes too long to complete especially for large circuit designs
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing delay values for library cells across multiple process corners and modes before the actual synthesis optimization begins. This pre-computation creates lookup tables that allow the optimizer to quickly assess timing impacts without performing full timing analysis during each iterative trial, thereby maintaining timing constraint satisfaction while dramatically reducing optimization time.
2Device complexity
If linear delay models are used for cell sizing, then the optimization process is simplified, but the model accuracy is insufficient leading to many timing violations
Solution Approach 1:
The patent applies parameter changes by transitioning from a simple linear delay model to a more accurate delay model that incorporates multiple parameters including process corner variations, mode-specific behaviors, and cell size dependencies. The patent computes delay values as functions of these parameters and stores them in lookup tables, allowing the synthesis tool to accurately predict timing behavior while maintaining computational efficiency through pre-computation.
3Measurement precision
If comprehensive timing analysis is performed across many process corners and modes, then timing constraint accuracy is improved, but the computational time increases significantly
Solution Approach 1:
The patent performs preliminary action by pre-computing delay values for all library cells across all process corners and modes before synthesis begins. These pre-computed values are stored in lookup tables organized by process corner, mode, and cell type. During actual synthesis, the tool simply queries these tables rather than performing comprehensive timing analysis, achieving both high accuracy and fast computation.
Solution Approach 2:
The patent applies partial action by computing and storing only the specific delay parameters needed for the numerical optimization process, rather than performing complete timing analysis for every possible scenario. The lookup tables contain pre-computed delay values for the relevant process corners and modes, providing sufficient accuracy for optimization without the computational burden of exhaustive timing analysis.
Data Source
AI summary
Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively.