Library Characterization via Circuit Pruning and Vector Segmentation
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Solution Overview
Problem
The process of library characterization for integrated circuit design is highly compute-intensive, requiring hundreds of machines running simulations in parallel for weeks or months, which delays the design schedule and increases computational intensity with the number of transistors and process variations.
Innovation Solution
The method involves determining and selecting distinct vectors for circuit arcs, performing circuit pruning to identify active circuits, and conducting simulations only on active transistors with significant influence, using a Response Surface Method (RSM) to reduce the number of simulations needed, thereby accelerating the characterization process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive library characterization is performed covering all process variations, then accuracy of electrical models is improved, but computational time and resources increase significantly
Solution Approach 1:
The patent segments the comprehensive set of process variations into distinct groups or categories. By dividing the full variation space into manageable segments, the methodology can selectively characterize only the most impactful segments rather than exhaustively simulating every possible variation, thus reducing computational time while maintaining model accuracy.
Solution Approach 2:
The patent changes the parameter space by identifying and focusing on critical process parameters that have the most significant impact on circuit behavior. By transforming the comprehensive parameter set into a reduced set of influential parameters, the methodology achieves accurate electrical models with fewer simulations, thereby reducing computational time and resources.
2Adaptability or versatility
If the number of transistors and process variations increases, then comprehensiveness of library characterization is improved, but computational intensity increases
Solution Approach 1:
The patent applies partial action by performing characterization on a selected subset of process variations and transistor combinations rather than exhaustively analyzing all possibilities. By identifying and characterizing only the most critical or representative cases, the methodology achieves sufficient comprehensiveness for design purposes while significantly reducing computational intensity.
Solution Approach 2:
The methodology transforms the high-dimensional parameter space created by multiple transistors and process variations into a reduced parameter space by identifying dominant factors. This parameter transformation allows comprehensive characterization of essential behavior without the exponential computational cost of analyzing all possible combinations.
3Reliability
If extensive circuit simulations are performed for all vectors, then completeness of electrical model is improved, but productivity decreases
Solution Approach 1:
The patent performs preliminary analysis to identify critical vectors and process variations before conducting full circuit simulations. By pre-screening the simulation space to determine which vectors and parameters have the most significant impact on electrical model accuracy, the methodology ensures completeness of essential model data while avoiding unnecessary simulations that would slow down the design process.
Solution Approach 2:
The methodology performs partial simulation by focusing computational resources on the most impactful vectors and process variations rather than exhaustively simulating all possible cases. This selective approach maintains the reliability and completeness of essential electrical model characteristics while significantly improving design productivity by reducing overall simulation time.
Data Source
AI summary
A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.